參數(shù)資料
型號： M37640E8
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
中文描述： 單芯片8位CMOS單片機(jī)
文件頁數(shù)： 95/172頁
文件大?。?/td> 1193K
代理商： M37640E8
7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
Timers
7/9/98
2-83
Figure 2-104. TXM Register
Read Method
When reading Timer X, the high-order byte is read first. Reading the high-order byte causes the values of
Timer XH and Timer XL to be placed in temporary registers assigned the same addresses as Timer XH and
Timer XL. The low-order byte of Timer X is then read from its temporary register. This operation assures
the correct reading of Timer X while it is counting.
2.13.1.2
Count Stop Control
If the Timer X Count Stop Bit (TXM7) (bit 7 of the TXM) is set to a “1”, Timer X stops counting
in all four modes.
2.13.1.3
Timer Mode
Count Source:
Φ
/
n
(where
n
is 8, 16, 32, or 64) or
SCSGCLK
In this mode, each time the timer underflows, the corresponding timer interrupt request bit is set to a
“1”, the contents of the timer latch are loaded into the timer, and the count down sequence begins again.
2.13.1.4
Pulse Output Mode
Φ
/
n
(where
n
is 8, 16, 32, or 64) or
SCSGCLK
Count Source:
Each time the timer X underflows, the output of the CNTR0 pin is inverted, and the corresponding
Timer X interrupt request bit is set to a “1”. The repeated inversion of the CNTR0 pin output
produces a rectangular waveform with a duty ratio of 50 percent. The initial level of the output is
determined by the CNTR0 polarity select bit (bit 6). When this bit is low, the output starts from a
high level. When this bit is high, the output starts from a low level.
TXM0
Timer X Data Write Control Bit (bit 0)
0: Write data in latch and timer
1: Write data in latch only
Timer X Frequency Division Ratio Bits (bits 2,1)
Bit 2
Bit 1
0
0:
0
1:
1
0:
1
1:
Timer X Internal Clock Select (bit 3)
0:
Φ
/n
1: SCSGCLK (from chip special count source generator)
Timer X Mode Bits (bits 5,4)
Bit 5
Bit 4
0
0:
Timer Mode
0
1:
Pulse output mode
1
0:
Event counter mode
1
1:
Pulse width measurement mode
CNTR0 Polarity Select Bit (bit 6)
0: For event counter mode, clocked by rising edge
For pulse output mode, start from high level output
For CNTR0 interrupt request, falling edge active
For pulse width measurement mode, measure high period
1: For event counter mode, clocked on falling edge
For pulse output mode, start from low level output
For CNTR0 interrupt request, rising edge active
For pulse width measurement mode, measure low period
Timer X Stop Bit (bit 7)
0: Count start
1: Count stop
TXM2,1
Φ
divided by 8
Φ
divided by 16
Φ
divided by 32
Φ
divided by 64
TXM3
TXM5,4
TXM6
TXM7
MSB
7
LSB
0
TXM7
TXM6
TXM5
TXM4
TXM3
TXM2
TXM1
TXM0
Access: R/W
Reset: 00
16
Address: 0027
16
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