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參數(shù)資料
| 型號： | M37640E8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER |
| 中文描述： | 單芯片8位CMOS單片機(jī) |
| 文件頁數(shù)： | 74/172頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | M37640E8 |
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2-62
7/9/98
Universal Serial Bus
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
OUTXCSR4
(FORCE_STALL): The USB FCU sets this bit to a “1” if the host sends out a larger
data packet than the MAXP size. The USB FCU returns a STALL handshake while this bit is set. The
CPU writes a “0” to clear this bit.
OUTXCSR5
(DATA_ERR): The USB FCU sets this bit to a “1” to indicate a CRC error or a bit
stuffing error received in an ISO packet. The CPU writes a “0” to clear this bit.
OUTXCSR6
(FLUSH): The CPU writes a “1” to this to flush the OUT FIFO. If there is one packet
in the OUT FIFO, a flush will cause the OUT FIFO to be empty, if there are two packets in the
OUT FIFO, a flush will cause the older packet to be flushed out from the OUT FIFO. Setting the
OUTXCSR6 (FLUSH) bit during reception could produce unpredictable results.
OUTXCSR7
(AUTO_CLR): If the CPU sets this bit to a “1”, the OUT_PKT_RDY bit is cleared
automatically by the USB FCU after the number of bytes of data equal to the maximum packet size
(MAXP) is unloaded from the OUT FIFO (see Chapter 2.9.3.2. Out (Receive) FIFOs for details).
Figure 2-77. USB Endpoint x OUT CSR
The
USB Endpoint x IN MAXP
, shown in Figure 2-78, indicates the maximum packet size (MAXP)
of an Endpoint x IN packet. The default value for Endpoint 0 is 8 bytes, the default values for
Endpoints 1-4 are 0 bytes. The CPU can change this value, as negotiated with the host controller
through the SET_DESCRIPTOR command.
Figure 2-78. USB Endpoint x IN MAXP
The
USB Endpoint x OUT MAXP
, shown in Figure 2-79, indicates the maximum packet size
(MAXP) of an Endpoint x OUT packet. The default values for endpoints 1-4 are 0 bytes. The CPU
can change this value, as negotiated with the host controller through the SET_DESCRIPTOR command.
For endpoint 0, all bits in this register are reserved: Endpoint 0 uses IN MAXP register for both IN
and OUT transfers.
OUTXCSR0
OUT_PKT_RDY Flag (bit 0) (Write “0” only or Read)
0: Out packet is not ready
1: Out packet is ready
OVER_RUN Flag (bit 1) (Write “0” only or Read)
0: No FIFO overrun
1: FIFO overrun occurred
SEND_STALL Bit (bit 2)
0: No action
1: Stall OUT Endpoint X by the CPU
ISO Bit (bit 3)
0: Select non-isochronous transfer
1: Select isochronous transfer
FORCE_STALL Flag (bit 4) (Write “0” only or Read)
0: No action
1: Stall Endpoint X by the USB FCU
DATA_ERR Flag (bit 5) (Write “0” only or Read)
0: No error
1: CRC or bit stuffing error received in an ISO packet
FLUSH Bit (bit 6) (Write Only - Read “0”)
0: No action
1: Flush the FIFO
AUTO_CLR Bit (bit 7)
0: AUTO_CLR disabled
1: AUTO_CLR enabled
OUTXCSR1
OUTXCSR2
OUTXCSR3
OUTXCSR4
OUTXCSR5
OUTXCSR6
OUTXCSR7
MSB
7
LSB
0
OUTXCSR7 OUTXCSR6 OUTXCSR5 OUTXCSR4 OUTXCSR3
OUTXCSR1 OUTXCSR0
Access: R/W
Reset: 00
16
OUTXCSR2
Address: 005A
16
IMAXP7:0
Maximum packet size (MAXP) of Endpoint x IN packet.
MAXP = n for endpoints 0, 2, 3, 4
MAXP = n * 8 for endpoint 1
n is the value written to this register. For endpoints that support a smaller
FIFO size, unused bits are not implemented (always write “0” to those bits)
MSB
7
LSB
0
IMAXP7
IMAXP6
IMAXP5
IMAXP4
IMAXP3
IMAXP1
IMAXP0
Access: R/W
IMAXP2
Address: 005B
16
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