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參數(shù)資料
| 型號： | M37640E8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER |
| 中文描述： | 單芯片8位CMOS單片機 |
| 文件頁數(shù)： | 72/172頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | M37640E8 |
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2-60
7/9/98
Universal Serial Bus
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Figure 2-74. USB Endpoint 0 IN CSR
The
USB Endpoint x IN CSR
((Control & Status Register), shown in Figure 2-75, contains control
and status information of the respective IN endpoint 1-4. The specific endpoint is selected by the
USB Endpoint Index Register.
INXCSR0
(IN_PKT_RDY) and
INXCSR5
(TX_FIFO_NOT_EMPTY): These two bits are read
together to determine IN FIFO status. A “1” can be written to the INXCSR0 bit by the CPU to
indicate a packet of data is written to the FIFO (See Chapter 2.9.3.1. IN (Transmit) FIFOs for detail).
INXCSR1
(UNDER_RUN) This bit is used in ISO mode only to indicate to the CPU that a FIFO
underrun has occurred. The USB FCU sets this bit to a “1” at the beginning of an IN token if no data
packet is in the FIFO. Setting this bit will cause the INST12 bit of the Interrupt Status Register 2 to
set. The CPU writes a “0” to clear this bit.
INXCSR2
(SEND_STALL): The CPU writes a “1” to this bit when the endpoint is stalled
(transmitter halt). The USB FCU returns a STALL handshake while this bit is set. The CPU writes a
“0” to clear this bit.
INXCSR3
(ISO): The CPU writes a “1” to this bit to initialize the respective endpoint as an
isochronous endpoint for IN transactions.
INXCSR4
(INTPT): The CPU writes a “1” to this bit to initialize this endpoint as a status change
endpoint for IN transactions. This bit is set only if the corresponding endpoint is to be used to
communicate rate feedback information (see Chapter 2.9.3.1. IN (Transmit) FIFOs for details).
INXCSR5
(TX_FIFO_NOT_EMPTY): The USB FCU sets this bit to a “1” when there is data in the
IN FIFO. This bit in conjunction with IN_PKT_RDY bit will provide the transmit FIFO status
information (see Chapter 2.9.3.1. IN (Transmit) FIFOs for details).
INXCSR6
(FLUSH): The CPU writes a “1” to this bit to flush the IN FIFO. If there is one packet in
the IN FIFO, a flush will cause the IN FIFO to be empty, if there are two packets in the IN FIFO, a
flush will cause the older packet to be flushed out from the IN FIFO. Setting the INXCSR6 (FLUSH)
bit during transmission could produce unpredictable results.
IN0CSR0
OUT_PKT_RDY Flag (bit 0) (Read Only - Write “0”)
0: Out packet is not ready
1: Out packet is ready
IN_PKT_RDY Bit (bit 1) (Write “1” only or Read)
0: In packet is not ready
1: In packet is ready
SEND_STALL Bit (bit 2) (Write “1” only or Read)
0: No action
1: Stall Endpoint 0 by the CPU
DATA_END Bit (bit 3) (Write “1” only or Read)
0: No action
1: Last packet of data transferred from/to the FIFO
FORCE_STALL Flag (bit 4) (Write “0” only or Read)
0: No action
1: Stall Endpoint 0 by the USB FCU
SETUP_END Flag (bit 5) (Read Only - Write “0”)
0: No action
1: Control transfer ended before the specific length of data is transferred during
the data phase
SERVICED_OUT_PKT_RDY Bit (bit 6) (Write Only - Read “0”)
0: No change
1: Clear the OUT_PKT_RDY bit (IN0CSR0)
SERVICED_SETUP_END Bit (bit 7) (Write Only - Read “0”)
0: No change
1: Clear the STUP_END bit (IN0CSR5)
IN0CSR1
IN0CSR2
IN0CSR3
IN0CSR4
IN0CSR5
IN0CSR6
IN0CSR7
MSB
7
LSB
0
IN0CSR7
IN0CSR6
IN0CSR5
IN0CSR4
IN0CSR3
IN0CSR1
IN0CSR0
Access: R/W
Reset: 00
16
IN0CSR2
Address: 0059
16
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