參數(shù)資料
型號: M37640E8
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
中文描述: 單芯片8位CMOS單片機
文件頁數(shù): 92/172頁
文件大?。?/td> 1193K
代理商: M37640E8
2-80
7/9/98
Special Count Source Generator
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Figure 2-102. Timer Count Operation for SCSG1
2.12.2 SCSG Description
2.12.2.1
SCSG1
SCSG1 is an 8-bit timer that has an 8-bit reload latch, and is a normal count down timer.
Write Method
When writing to the timer, the data is placed in the SCSG1 reload latch. At this point, if the SCSG1
Data Write Control Bit (SCSGM0) is “0”, the value in the SCSG1 reload latch is also loaded in
SCSG1. If SCSGM0 is “1”, the data in the SCSG1 reload latch is loaded in SCSG1 after SCSG1
underflows.
SCSG1 Count Stop Control
If the SCSG1 Count Stop Bit (SCSGM1) (bit 1 of the SCSGM Register) is set to a “1”, SCSG1 stops
counting. This allows
Φ
to bypass SCSG1 and act as the clock source for SCSG2. If the
SCSGCLK
Output Control Bit (SCSGM3) is cleared to “0”,
SCSGCLK
is disabled and SCSG1 stops counting (see
Figure 2-103.).
2.12.2.2
SCSG2
SCSG2 is an 8-bit timer that has an 8-bit reload latch, and is a normal count down timer.
Write Method
When writing to the timer, the data is placed in the SCSG2 reload latch. At this point, if the SCSG2
Data Write Control Bit (SCSGM2) is low, the value in the SCSG2 reload latch is also loaded in
SCSG2. If SCSGM2 is high, the data in the SCSG2 reload latch is loaded in SCSG2 after SCSG2
underflows.
Figure 2-103. SCSGM Register
Count Source
SCSG1 Contents
SCSG1 Underflow
SCSG1 Latch Contents
SCSG1 reload latch contents loaded into SCSG1
1
0
n
n
-1
1
0
m m-1
n
m
MSB
7
LSB
0
SCSGM3
SCSGM1
SCSGM0
SCSGM0
SCSG1 Data Write Control Bit (bit 0)
0: Write data in latch and timer
1: Write data in latch only
SCSG1 Count Stop Bit (bit 1)
0: Count start
1: Count stop
SCSG2 Data Write Control Bit (bit 2)
0: Write data in latch and timer
1: Write data in latch only
SCSGCLK Output Control Bit (bit 3)
0: SCSGCLK output disabled (SCSG1 and SCSG2 off)
1: SCSGCLK output enabled.
Reserved (Read/Write “0”)
SCSGM1
SCSGM2
SCSGM3
Bits 4-7
Access: R/W
Reset: 00
16
SCSGM2
Address: 002F
16
Reserved
Reserved
Reserved
Reserved
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