
7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
Universal Serial Bus
7/9/98
2-51
Figure 2-63. USB Function Control Unit Block Diagram
2.9.2
USB Interrupts
There are two types of USB interrupts in this device: the first type is the USB function (including
overrun/underrun, reset, suspend and resume) interrupt, used to control the flow of data and USB power
control; the second type is start-of-frame (SOF) interrupt, used to monitor the transfer of isochronous
(ISO) data.
2.9.2.1
USB Function Interrupt
Endpoint 1-4, each has two interrupt status bits associated with it to control the data transfer or to
report a STALL/UNDER_RUN/OVER_RUN condition. The EPx_OUT_INT bit is set when the USB
FCU successfully receives a packet of data, or sets the FORCE_STALL bit, or the OVER_RUN bit of
the Endpoint x OUT CSR. The EPx_IN_INT bit is set when the USB FCU successfully sends a packet
of data, or sets the UNDER_RUN bit of the Endpoint x IN CSR. Endpoint 0 - the control endpoint -
has one interrupt status bit associated with it to control the data transfer or report a STALL condition.
The EP0_INT is set when the USB FCU successfully receives/sends a packet of data, or sets the
SETUP_END bit, the FORCE_STALL bit, or clears the DATA_END bit in the Endpoint 0 IN CSR.
Each endpoint interrupt is enabled by setting the corresponding bit in the USB Interrupt Enable
Register 1 and 2. The USB Interrupt Status Register 1 and 2 are used to indicate pending interrupts
for a given endpoint. The USB FCU sets the interrupt status bits. The CPU writes a “1” to clear the
corresponding status bit. By writing back the same value it read, the CPU will clear all the existing
interrupts. The CPU must read then write both status registers, writing status register 1 first and status
register 2 second to guarantee proper operation.
The suspend interrupt status bit is set if a USB suspend signaling is received. If the device is in
suspend mode, the resume interrupt status bit is set when a USB resume signaling is received. There is
a single interrupt enable bit for both of suspend and resume interrupts (bit 7 of the interrupt enable
register 2).
The USB reset interrupt status bit is set if a USB reset signaling is received. When this bit is set, all
USB internal registers will be reset to their default values except this bit itself. This bit is cleared by
the CPU writing a “0” to it. When the CPU detects a USB reset interrupt, it needs to re-initialize the
USB block in order to accept packets from the host.
CPU
MCI
SIU
GFI
FIFOs
SIE
T
D
+
D
-