- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370847 > M37640E8 (Mitsubishi Electric Corporation) SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER PDF資料下載
參數(shù)資料
| 型號： | M37640E8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER |
| 中文描述： | 單芯片8位CMOS單片機 |
| 文件頁數(shù)： | 83/172頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | M37640E8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁當前第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁
7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
Direct Memory Access Controller
7/9/98
2-71
2.11.1.1
Source, Destination, and Transfer Count Register Operation
The user can choose whether the source and destination register for each channel will increment by
one, decrement by one, or remain unchanged after each transfer by setting bits 0 through 3 (DxSRID,
DxSRCE, DxDRID, and DxDRCE) of DMAC Channel x Mode Register 1 (DMAxM1) to the
appropriate values. The values in the source and destination registers are updated with their reload latch
values when the transfer count register underflows. The transfer count register is also reloaded when it
underflows, and both a flag (DxUF) and the DMAC interrupt associated with the channel are set.
Reload of the source and destination registers due to underflow of the transfer count register can be
disabled by setting to “1” the DMAC Register Reload Disable Bit (DRLDD). This bit affects reload for
both channel 0 and channel 1.
Because the transfer count register is 16-bits wide, up to 65,536 transfers can take place before an
underflow and the resulting actions described above occur. If the Channel x Disable After Count
Register Underflow Enable Bit (DxDAUE) is set to a “1”, then the Channel x Enable Bit (DxCEN) is
cleared to a “0” when the transfer count register underflows, disabling channel x of the DMAC.
The source, destination, and transfer count registers of a DMAC channel can be updated with their
reload latch value at any time by setting to a “1” the DMAC Channel x Register Reload Bit (DxRLD).
DMAC Source, Destination, and Transfer Count Register Read and Write Method
Read and write operations on the high and low-order bytes of the source, destination, and transfer
count registers must be performed in a specific order.
Write Method
When writing to the source, destination, or transfer count register, the low-order byte is written first.
Next, the high-order byte is written. When this is done, the data is placed in the reload latch of the
high-order byte of the register and the previously written low-order byte data is placed in the reload
latch of the low-order byte. At this point, if the DMAC Channel x Write Control Bit (DxDWC) is
“0”, the values in the reload latches are also loaded in the low and high-order bytes of the register.
If DxDWC is “1”, the data in the reload latches are loaded in the register after the transfer count
register of the DMAC channel underflows or the DxRLD bit of the DMAC channel is set to a “1”.
Read Method
When reading from the source, destination, or transfer count register, the high-order byte is read
first. The low-order byte of the register is then read. The value read from the low-order byte of the
register is its value when the high-order byte was read.
2.11.1.2
DMAC Transfer Request Sources
The hardware source for initiating a DMAC transfer for each channel is selectable by setting the
DMAC Channel x Hardware Transfer Request Source Bits (DxHRS0, 1, 2, 3) to appropriate values.
The choices for channel 0 are the UART1 receive or transmit interrupts, the TimerY interrupt, external
interrupt 0, one of three USB endpoint OUT_PKT_RDY signals, one of three USB endpoint
IN_PKT_RDY signals, the USB endpoint 1 OUT_FIFO_NOT_EMPTY signal, the OBE0 and IBF0
(data) signals from the MBI, the SIO combined receive/transmit interrupt, and the CNTR1 interrupt.
The choices for channel 1 are the UART2 receive and transmit interrupts, the TimerX interrupt,
external interrupt 1, one of three USB endpoint OUT_PKT_RDY signals, one of three USB endpoint
IN_PKT_RDY signals, the USB endpoint 1 OUT_FIFO_NOT_EMPTY signal, the OBE1 and IBF1
(data) signals from the MBI, the Timer1 interrupt, and the CNTR0 interrupt.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37641F8-XXXFP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37641F8-XXXHP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37641M8-XXXFP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37641M8 | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37641F8FP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37640E8FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37640E8FS | 功能描述:EPROM MCU/8BIT CMOS EMULATION CH RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 配件 系列:- 標準包裝:1 系列:- 附件類型:適配器板 適用于相關(guān)產(chǎn)品:RCB230，RCB231，RCB212 配用:26790D-ND - RCB BREAKOUT BOARD RS232 CABLE |
| M37640M4T | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37640M8-111FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37640M8-126FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。