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參數(shù)資料
| 型號(hào)： | M37640E8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER |
| 中文描述： | 單芯片8位CMOS單片機(jī) |
| 文件頁(yè)數(shù)： | 84/172頁(yè) |
| 文件大小： | 1193K |
| 代理商： | M37640E8 |
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7/9/98
Direct Memory Access Controller
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
In addition, each channel has a software trigger that can initiate a DMAC transfer. The software trigger
is set by writing a “1” to the DMAC Software Transfer Trigger (DxSWT). The hardware transfer
request source for each channel can be disabled by writing a “0” to DxHRS0, 1, 2, and 3. When these
bits are all “0”, which is the reset state, only the software trigger can be used to initiate a transfer.
The initiating source for each channel is latched by the DMAC asynchronously and sampled on the
rising edge of
Φ
. Writing a “1” to the DMAC Channel x Transfer Initiation Source Capture Register
Reset bit (DxCRR) causes the initiating source sample latch of the associated DMAC channel to be
reset. The sample latch is reset automatically one cycle of
Φ
after a transfer request is detected. New
transfer requests for a channel that occur during a DMAC transfer by that same channel are latched as
long as they occur after the sample latch is reset. However, if multiple transfer requests occur during a
transfer, only one transfer request will be registered.
If an interrupt is chosen as the initiating source for DMAC transfers, its interrupt control bit located in
one of the three interrupt control registers of the ICU should be cleared to “0” if the user does not
wish to have the interrupt serviced by the CPU.
2.11.1.3
Transfer Features for USB and MBI
In order to make the transfer of data between the USB endpoint FIFOs and the input and output
buffers of the MBI more efficient, special features have been included in the transfer request logic of
each DMAC channel. These features are enabled for a channel when one of the USB endpoint signals
is selected as the hardware transfer request source and the DMAC Channel x USB and MBI Enable
Bit (DxUMIE) is set to a “1”. These features are only intended to be used with single-byte transfer
mode.
USB OUT FIFO to MBI Output Buffer Transfers
The special features provided by both DMAC channels for transfer of data from a USB OUT FIFO
to one of the MBI output buffers help facilitate either packet-by-packet transfers or byte-by-byte
transfers.
Packet-by-Packet Transfers
When a USB endpoint OUT_PKT_RDY signal is selected as the hardware transfer request source for
a DMAC channel and the DxUMIE bit of the same channel is set to a “1”, a transfer request is
generated for that DMAC channel when the OUT_PKT_RDY signal for the chosen USB endpoint is
high and output buffer x (where x is “0” for DMAC channel 0 and “1” for DMAC channel 1) of
the MBI is empty. The OUT_PKT_RDY signal remains high until all bytes of the packet have been
read from the OUT FIFO corresponding to that endpoint. Thus, the first transfer request is generated
when the OUT_PKT_RDY signal goes high and subsequent transfer requests are generated each time
output buffer x becomes empty. Once the final byte of the received packet has been read, the
OUT_PKT_RDY signal automatically goes low (if this option is enabled in the USB block). This in
turn causes the source, destination, and transfer count registers of the involved DMAC channel to be
reloaded (unless the DRLDD bit is set to a “1”) and the DMAC interrupt for the involved channel
to be set. In addition, if the DxDAUE bit associated with the channel is “1”, the channel’s DxCEN
bit is automatically cleared to “0”, disabling the channel.
This feature allows a channel of the DMAC in single-byte transfer mode to automatically transfer a
received packet of an endpoint from the endpoint’s OUT FIFO to the master CPU (via the MBI)
without any intervention by the on-chip CPU. Also, because the source, destination, and transfer
count registers are automatically reloaded once the current packet has been completely transferred,
on-chip CPU intervention is not needed to set up the DMAC channel for transfer of subsequently
received packets, even in the case of reception of a short packet.
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| M37641F8-XXXFP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37641F8-XXXHP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37641M8-XXXFP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| M37640E8FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37640E8FS | 功能描述:EPROM MCU/8BIT CMOS EMULATION CH RoHS:否 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 配件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 附件類型:適配器板 適用于相關(guān)產(chǎn)品:RCB230，RCB231，RCB212 配用:26790D-ND - RCB BREAKOUT BOARD RS232 CABLE |
| M37640M4T | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37640M8-111FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37640M8-126FP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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