
7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
UART
7/9/98
2-99
2.14.8 Clear-to Send (CTSx) and Request-to-Send (RTSx) Signals
The UART, as a transmitter, can be configured to recognize the Clear-to-Send (CTSx) input as a
handshaking signal. As a receiver, the UART can be configured to generate the Request-to-Send
(RTSx) handshaking signal.
Clear-to-Send (
CTSx
) Input
CTS handshaking is enabled by setting the Clear-to-Send Enable Bit (CTS_SEL, bit 5 of UxCON) to a
“1”. If CTS handshaking is enabled, when TEN is a “1” and the low-order byte of the transmit buffer
(UxTRB1) is loaded, the UART begins the transmission process when the CTSx pin is asserted (low
input). After beginning a send operation, the UART does not stop sending until the transmission is
completed, even if CTSx is deasserted (high input). If TEN is cleared to “0”, the UART will not stop
transmitting and the port pins will remain under the control of the UART until the end of the
transmission. If CTS handshaking is disabled and TEN is a “1”, the UART begins the transmission
process as soon as data is available in the low-order byte of the transmit buffer (UxTRB1). Figure 2-
115 shows a timing example for CTSx.
Request-to-Send (
RTSx
) Output
RTS handshaking is enabled by setting the Request-to-Send Enable Bit (RTS_SEL, bit 6 of UxCON) to
a “1”. When RTS handshaking is enabled, the UART drives the RTSx output low or high based on
the following conditions:
Assertion conditions (driven low):
The Receive Enable Bit (REN) is set to a “1”.
Receive operation has completed with the reception of the last stop bit, REN is still a “1”, and
the programmable assertion delay has expired.
De-assertion conditions (driven high):
A valid start bit is detected and REN is a “1”.
REN is cleared to a “0” before a receive operation is in progress.
Receive operation has completed and REN is a “0”.
UART Receiver is initialized (RIN is set to a “1”).
The delay time from the reception of the last stop bit to the re-assertion of RTSx is programmable.
The amount of delay is selected by setting the RTS Assertion Delay Count Bits (RTS3~0, bits 3 to 0
of UxRTSC) (see Figure 2-114). The time can be from no delay to 120 bit-times, with the delay
beginning from the middle of the last stop bit. If a start bit is detected before the assertion delay has
expired, the delay countdown is stopped and the RTSx pin remains high. A full assertion delay
countdown will begin again once the last stop bit of the incoming data has been received. Figure 2-115
shows a timing example for RTSx.