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參數(shù)資料
| 型號(hào)： | M37640E8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER |
| 中文描述： | 單芯片8位CMOS單片機(jī) |
| 文件頁(yè)數(shù)： | 91/172頁(yè) |
| 文件大小： | 1193K |
| 代理商： | M37640E8 |
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7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
Special Count Source Generator
7/9/98
2-79
2.12 Special Count Source Generator
This device has a built-in special count source generator. It consists of two 8-bit timers: SCSG1, and
SCSG2 (see Figure 2-101.) The contents of the timer latch, corresponding to each timer, determine the
divide ratio. The timers can be written to at any time. The output of the special count source generator
can be a clock source for Timer X, SIO and the two UARTs.
Figure 2-101. SCSG Block Diagram
2.12.1 SCSG Operation
The SCSG1 and SCSG2 are both down count timers. When the count of a timer reaches 00
16
, an
underflow occurs at the next count pulse and the contents of the corresponding timer reload latch are
loaded into the timer. For the count operation for SCSG1 with the Data Write Mode set to write to
the latch only see (Figure 2-102.).
A memory map and the initial values after reset of the timers and timer reload latches are detailed
above. The divide ratio of each timer is given by 1/(
n
+ 1), where
n
is the value written to the timer.
The output of the first timer (SCSG1) is effectively ANDed with the original clock (
Φ
) to provide a
count source for the second timer (SCSG2). This results in a count source of
n
/(
n
+ 1) being fed to
SCSG2.
The output of the SCSG is a clock,
SCSGCLK
. The frequency is calculated as follows:
SCSG
1
1
+
SCSG
2
1
+
where SCSG1 is the value written to SCSG1 and SCSG2 is the
value written to SCSG2.
Address
Description
Acronym and
Value at Reset
002D
16
002E
16
002F
16
Special Count Source Generator1
Special Count Source Generator2
Special Count Source mode register
SCSG1=FF
SCSG2=FF
SCSM=00
Φ
SCSGM1
SCSGM3
SCSG1 Reload Latch (8)
SCSG1 (8)
SCSGM1
SCSGM1
SCSGM3
SCSGM0
SCSGM2
SCSG2 Reload Latch (8)
SCSGM3
SCSGCLK
(To UARTs, Timer X and SIO)
SCSG2 (8)
SCSGCLK
Φ
-------------------1
-----------1
=
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