參數(shù)資料
型號: M37640E8
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
中文描述: 單芯片8位CMOS單片機
文件頁數(shù): 70/172頁
文件大?。?/td> 1193K
代理商: M37640E8
2-58
7/9/98
Universal Serial Bus
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
The
USB Frame Number Low Register
, shown in Figure 2-71, contains the lower 8 bits of the 11-bit
frame number received from the host. The
USB Frame Number High Register
, shown in Figure 2-72
contains the upper 3 bits of the 11-bit frame number received from the host.
Figure 2-71. USB Frame Number Low Register
Figure 2-72. USB Frame Number High Register
The
USB Endpoint Index Register,
shown in Figure 2-73, identifies the endpoint pair. It serves as an
index to endpoint-specific IN CSR, OUT CSR, IN MAXP, OUT MAXP and OUT WRT CNT
registers.
This register also contains two global bits, ISO_UPD and AUTO_FL for endpoints 1-4 regarding the
isochronous data transfer.
If ISO_UPD = “0”, a data packet in an endpoint’s IN FIFO is always ‘ready to transmit’ upon
receiving the next IN_TOKEN from the host (with matched address & endpoint number). If ISO_UPD
= “1” and the ISO bit of the corresponding endpoint’s IN CSR is set, then the internal ‘ready to
transmit’ signal to the transmit control logic is delayed until the next SOF. In this way the data loaded
in frame n will be transmitted out in frame n+1. The ISO_UPD bit is a global bit for endpoints 1 to
4, and works with isochronous pipes only.
If AUTO_FL = “1”, ISO_UPD = "1", and a particular IN endpoint’s ISO bit is set, then at the time
the USB FCU detects a SOF packet, if the corresponding IN endpoint’s IN_PKT_RDY = “1”, the USB
FCU automatically flushes the oldest packet from the IN FIFO. In this case, IN_PKT_RDY = “1”
indicates that two data packet are in the IN FIFO. Since, for ISO transfer, double buffering is a
requirement, MAXP must set to be less than or equal to 1/2 of the FIFO size.
Figure 2-73. USB Endpoint Index Register
The
Endpoint 0 IN CSR
(Control & Status Register), shown in Figure 2-74, contains the control and
status information of Endpoint 0.
FN7:0
Lower 8 bits of the 11-bit frame number issued with a SOF token
MSB
7
LSB
0
FN7
FN6
FN5
FN4
FN3
FN1
FN0
Access: R
Reset: 00
16
FN2
Address: 0056
16
FN10:8
Upper 3 bits of the 11-bit frame number issued with a SOF token
Bits 7:3
Reserved (Read “0”)
MSB
7
LSB
0
Reserved
Reserved
Reserved
Reserved
Reserved
FN9
FN8
Access: R
Reset: 00
16
FN10
Address: 0057
16
EPINDX2:0
Endpoint Index:
Bit 2
0
0
0
0
1
Others:
Bit 1
Bit 0
0
0
1
1
0
0:
1:
0:
1:
0:
Function Endpoint 0
Function Endpoint 1
Function Endpoint 2
Function Endpoint 3
Function Endpoint 4
Undefined
Bits 3:5
Reserved (Read/Write “0”)
AUTO_FL
AUTO_FLUSH Bit (bit 6)
0: Hardware auto FIFO flush disabled
1: Hardware auto FIFO flush enabled
ISO_UPDATE Bit (bit 7)
0: ISO_UPDATE disabled
1: ISO_UPDATE enabled
ISO_UPD
MSB
7
LSB
0
ISO_UPD
AUTO_FL
Reserved
Reserved
Reserved
EPINDX1
EPINDX0
Access: R/W
Reset: 00
16
EPINDX2
Address: 0058
16
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