
7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
Universal Serial Bus
7/9/98
2-53
MAXP <= half of the IN FIFO size: When the number of bytes of data equal to the MAXP
(maximum packet size) is written to the IN FIFO by the CPU/DMAC, the USB FCU sets the
IN_PKT_RDY bit to a ‘1’ automatically. The USB FCU clears the IN_PKT_RDY bit as soon as the
IN FIFO is ready to accept another data packet (The FIFO can hold up to two data packets at the
same time in this configuration, for back-to-back transmission). Since the set and the clear operations
could be as fast as 83ns (one 12MHz clock period) apart from each other, the set may be transparent
to the user.
A software or a hardware flush acts as if a packet is being successfully transmitted out to the host. If
there is one packet in the IN FIFO, a flush will cause the IN FIFO to be empty, if there are two
packets in the IN FIFO, a flush will cause the older packet to be flushed out from the IN FIFO. Flush
will update the IN FIFO status (IN_PKT_RDY and TX_NOT_EMPTY bits).
The status of the endpoint 1-4 IN FIFO for both of the above cases, could be obtained from the IN
CSR as follows:
Interrupt Endpoints:
Any endpoint can be used for interrupt transfers. For normal interrupt transfers,
the interrupt transactions behave the same as bulk transactions, i.e., no special setting is required. The
IN endpoints may also be used to communicate rate feedback information for certain types of
isochronous functions. This is done by setting the INTPT bit in the IN CSR register of the
corresponding endpoint. When the INTPT bit is set, the data toggle bits will be changed after each
packet is sent to the host without regard to the presence or type of handshake packet.
The following outlines the operation sequence for an IN endpoint used to communicate rate feedback
information:
1.
Set MAXP > 1/2 of the endpoint’s FIFO size;
2.
Set INTPT bit of the IN CSR;
3.
Flush the old data in the FIFO;
4.
Load interrupt status information and set IN_PKT_RDY bit in the IN CSR;
5.
Repeat steps 3 & 4 for all subsequent interrupt status updates.
2.9.3.2
Out (Receive) FIFOs
The USB FCU writes data to the endpoint’s OUT FIFO location specified by the FIFO write pointer,
which automatically increments by one after a write. When the USB FCU has successfully received a
data packet, it sets the OUT_PKT_RDY bit to a “1” in the OUT CSR. The CPU/DMAC should only
read data from the OUT FIFO if the OUT_PKT_RDY bit of the OUT CSR is a “1”, with the
exception of endpoint 1 (see detail description below).
Endpoint 0 OUT FIFO Operation
: The USB FCU sets the OUT_PKT_RDY bit to a ‘1’ after it has
successfully received a packet of data from the host. The CPU writes a “0” to the OUT_PKT_RDY bit
after the packet of data is unloaded from the OUT FIFO by the CPU.
Endpoint 1-4 OUT FIFO Operation when AUTO_CLR (bit 7 of OUT CSR) = “0”
:
IN_PKT_RDY
TX_NOT_EMPTY
TX FIFO Status
0
0
1
0
1
0
No data packet in TX FIFO
One data packet in TX FIFO if MAXP <= half of the FIFO size.
Invalid
Two data packets in TX FIFO if MAXP <= half of the FIFO size or
One data packet in TX FIFO if MAXP > half of the FIFO size
1
1