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參數(shù)資料
| 型號(hào)： | M37640E8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER |
| 中文描述： | 單芯片8位CMOS單片機(jī) |
| 文件頁(yè)數(shù)： | 82/172頁(yè) |
| 文件大?。?/td> | 1193K |
| 代理商： | M37640E8 |
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7/9/98
Direct Memory Access Controller
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
The 16-bit source and destination registers allow accesses to any two locations in the 64K byte
memory area. The 16-bit transfer count register decrements by one for each transfer performed and
causes an interrupt and flag to be set when it underflows. The mode registers control the
configuration and operation of the DMAC channel associated with the registers. A block diagram of
the DMAC is shown in Figure 2-93.
The SFR addresses for the two mode, source, destination, and transfer count registers of a channel are
the same for each channel. Which channel’s registers are accessible is determined by the value of the
DMAC Channel Index Bit (DCI) (bit 7 of the DMAC Index and Status Register (DMAIS)). When this
bit is a “0”, channel 0 registers are accessible, and when this bit is a “1”, channel 1 registers are
accessible. The configuration of DMAIS and the mode registers are shown in Figure 2-94, Figure 2-95,
Figure 2-96, and Figure 2-97.
Figure 2-93. DMAC Block Diagram
2.11.1 Operation
Each channel of the DMAC transfers byte data from a source address to a destination address when a
selected event occurs. If single-byte transfer mode is enabled, one byte of data is transferred per
request. If burst transfer mode is enabled, several bytes can be transferred per request, one byte at a
time. A temporary register internal to the DMAC stores the data read from the source address until it
is written to the destination address on the next cycle. The transfer of one byte takes two cycles of
Φ
and causes the CPU and possibly the other DMAC channel to stall during this time. At least one cycle
of
Φ
with the CPU operating must take place between transfers by the same DMAC channel caused
by different events or between transfers by the two DMAC channels. The DMAC does not operate
during WIT, STP, or Hold states.
0
15
Mode Reg 1
Mode Reg 2
Temp Reg
Ch 0 Count Latch
Data Bus
Ch 0 Timing Generator
Address Bus
Interrupts:TimerY, CNTR1
(D0CEN; D0CRR;
D0UMIE; D0SWT;
D0HRS3,2,1,0)
(DTSC)
(D0SRID,
D0RLD)
(D0DRID,
D0RLD)
DInterrupt
(D0DWC)
(D0DWC)
(D0DWC)
0
15
INT Detect, I-flag
Ch 0 Destination Latch
Ch 0 Destination Reg
0
15
Ch 0 Source Latch
Ch 0 Source Reg
(D0TMS)
(D0UF)
DMAC Channel 0
DMAC Channel 1
Index &
Status Reg
Data Bus
Signals:EP3 OUT_PKT_RDY or
IN_PKT_RDY,
INT Detect, I-flag
Interrupts: Timer1, TimerX, CNTR0
Signals:EP4 OUT_PKT_RDY or
IN_PKT_RDY,
(D0SFI)
(D1UF, D1SFI)
Ch 0 Count Reg
EP1 OUT_FIFO_NOT_EMPTY
EP1 OUT_FIFO_NOT_EMPTY
(D0DAUE)
Int
Gen
(DRLDD)
(DRLDD)
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| M37641F8-XXXFP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37641F8-XXXHP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37641M8-XXXFP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37641M8 | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37641F8FP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37640E8FP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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| M37640M4T | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37640M8-111FP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37640M8-126FP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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