參數(shù)資料
型號: M37640E8
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
中文描述: 單芯片8位CMOS單片機
文件頁數(shù): 21/172頁
文件大?。?/td> 1193K
代理商: M37640E8
7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
Oscillator Circuit
7/9/98
2-9
Figure 2-6. Clock Flow Diagram
Xin clock stopped
XCin clock on
PLL clock stopped
Φ
=f(XCin)/2
CPMA=BC, FSC=68
Xin clock stopped
XCin clock on
PLL clock on
Note 3
Φ
=f(XCin)/2
CPMA7=BC, FSC=49
Xin clock stopped
XCin clock on
Φ
=f(PLL)/2
CPMA7=FC, FSC=49
Xin clock on
XCin clock on
Φ
=f(PLL)/2
CPMA=DC, FSC=41
Xin clock on
XCin clock on
PLL clock on
Note 3
Φ
=f(XCin)/2
CPMA=9C, FSC=41
Xin clock on
XCin clock on
PLL clock stopped
Φ
=f(XCin)/2
CPMA=9C, FSC=60
Xin clock on
XCin clock on
PLL clock stopped
Φ
=f(Xin)/4
CPMA=1C, FSC=60
Xin clock on
XCin clock on
Note 3
Φ
=f(Xin)/4
Note 2
CPMA=1C, FSC=41
Xin clock on
XCin clock on
Φ
=f(PLL)/2
CPMA=5C, FSC=41
Xin clock on
XCin clock stopped
Φ
=f(PLL)/2
CPMA=4C, FSC=41
Stop
Note 1
Wait
Stop
Note 1
Wait
Stop
Note 1
Wait
Stop
Note 1
Wait
Wait
Wait
Wait
Wait
Reset
FSC0
1
CPMA6
1
1
0
CPMA4
CPMA7
CPMA5
Note 4
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
FSC0
FSC0
FSC0
CPMA6
CPMA6
CPMA6
Note:
CPMA values shown assume single-chip mode with stack in one page.
Xin clock on
XCin clock stopped
PLL clock stopped
Φ
=f(Xin)/4
CPMA=0C, FSC=60
Xin clock on
XCin clock stopped
Φ
=f(Xin)/4
Note 2
CPMA=0C, FSC=41
Note 1:
Stop mode stops the oscillators which are also the inputs to the frequency synthesizer.
However, the frequency synthesizer is not disabled and so its output is unstable. So, always
set the system clock to an external oscillator and disable the frequency synthesizer before
entering stop mode.
Note 2
: Φ
=f(X
)/4 can be inter-changed with
Φ
=f(X
in
)/2 by setting CCR7 to “1”. The same
flow-chart applies for both cases.
Note 3:
The input to the frequency synthesizer is independent of the system clock. It can be
either X
or XC
depending on bit 3 of FSC. In the above flow, the input has been chosen
to be the same as the system clock only for simplicity. The oscillator selected to be the input
to the frequency synthesizer must be enabled before the frequency synthesizer is enabled.
Note 4
:
The input clock for the frequency synthesizer must be set to XCin by setting FIN
(bit 3 of FSC) to a “1” before Xin oscillation can be disabled.
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