參數(shù)資料
型號： M37640E8
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
中文描述： 單芯片8位CMOS單片機(jī)
文件頁數(shù)： 59/172頁
文件大?。?/td> 1193K
代理商： M37640E8
7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
Interrupt Control Unit
7/9/98
2-47
2.8.2
Interrupt Sequence and Timing
The interrupts are polled prior to the beginning of each instruction. An interrupt service request is
generated when an interrupt event has its interrupt request bit set to a “1”, its interrupt enable bit is
set to a “1”, and the interrupt inhibit flag I is set low. The I flag is used to disable all maskable
interrupts. When this bit is set to a “1”, only a BRK instruction or a user Reset can cause an interrupt
service request to be generated. Figure 2-59 is a simplified version of the logic that controls whether
an interrupt service request is generated.
Figure 2-59. Interrupt Service Request Control Logic
The time elapsed from the occurrence of an interrupt event until execution of its service routine varies
from 7 cycles to 23 cycles, depending on what instruction is executing when the interrupt event occurs
(see Figure 2-60.)
Figure 2-60. Execution Time Prior to Interrupt Service Routine
When an interrupt service request occurs, the current instruction stream is temporarily halted and the
appropriate interrupt service routine is executed. After the interrupt service routine ends, the current
instruction stream is resumed with the next instruction.
The interrupt service request causes the MCU to automatically push the high-order byte of the program
counter, the low-order byte of the program counter, and the contents of the processor status register
onto the stack. A push consists of storing data at the stack address and decrementing the stack pointer
by one as illustrated in Figure 2-2. The I flag is set to a “1” to prevent other interrupts from being
serviced during the interrupt service routine, and the request bit corresponding to the interrupting event
is automatically cleared to “0”. The program counter is set to the address specified in the vector table
for the interrupt being serviced. This address contains the address for the first instruction of the
interrupt service routine. The timing for the pushing of data onto the stack, and fetching the starting
address of the interrupt routine is illustrated in Figure 2-61.
Interrupt Request Bit
Interrupt Enable Bit
Interrupt Inhibit Flag I
BRK Instruction
Reset
Interrupt Request
Interrupt Request
23 to 7 Cycles (1.92
μ
s to 0.583
μ
s, when f(
Φ
) = 12 MHz)
Maximum 16 cycles *
Minimum 0 cycles
2 cycles,
dummy cycles
for pipeline
postprocessing
5 cycles,
stack push
and
vector fetch
Interrupt Processing
Routine
Current Instruction
* For DIV Instruction
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