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參數(shù)資料
| 型號(hào)： | M37640E8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER |
| 中文描述： | 單芯片8位CMOS單片機(jī) |
| 文件頁(yè)數(shù)： | 12/172頁(yè) |
| 文件大?。?/td> | 1193K |
| 代理商： | M37640E8 |
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1-8
6/2/98
Pin Description and Layout
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
D+/D- Line driver notes:
In order to match the USB cable impedance, a series resistor of
33, 1%,
1/8
W should be connected to each USB line; i.e. on D+ (pin 70) and on D- (pin 71). Also, a
coupling capacitor with the recommended value of 33pF should be connected between D+ and D- after
the 33
series resistors. If the USB line is improperly terminated or not matched, signal fidelity will
suffer, resulting in excessive overshoot or undershoot. This will potentially introduce bit errors.
VDD/VSS notes:
In order to reduce the effects of the inductance of the traces on the board,
decoupling capacitors should be connected between pins 73(VSS) and 74(VDD), 13(VSS) and 16(VDD),
and 17(AVDD) and 19(AVSS). Recommended values are a 4.7
μ
F in parallel with a 0.1
μ
F.
Figure 1-3. VDD/VSS decoupling capacitor connections
P7
3
/IBF
1
/
HLDA
P7
4
/OBF
1
P8
0
/UTXD2/
SRDY
P8
1
/URXD2/
SCLK
P8
2
/CTS2/
SRXD
P8
3
/RTS2/
STXD
P8
4
/UTXD1 I/O CMOS I/O port or UART1 pin UTXD1.
P8
5
/URXD1 I/O CMOS I/O port or UART1 pin URXD1.
P8
6/
CTS1
I/O CMOS I/O port or UART1 pin CTS1.
P8
7
/RTS1
I/O CMOS I/O port or UART1 pin RTS1.
AV
cc
,AV
ss
I Power supply inputs for analog circuitry AV
cc
= 4.15~ 5.25V, AV
ss
= 0V
Controls the processor mode of the chip. Normally connected to V
ss
or V
cc
. When the MCU is in EPROM
program mode, this pin supplies the programming voltage to the EPROM.
I/Omutually exclusive. IBF
1
output to master CPU for data bus buffer 1, or HLDA pin. IBF
1
and HLDA are
1
has priority over HLDA.
I/O CMOS I/O port or OBF
1
output to master CPU for data bus buffer 1.
I/Opriority over SIO.
I/Ohas priority over SIO.
I/Opriority over SIO.
I/Opriority over SIO.
66
65
32
31
30
29
28
27
26
25
17,19
CNV
ss
I
9
V
cc
,V
ss
I Power supply inputs: V
cc
= 4.15~ 5.25V, V
ss
= 0V
16/74,
13/73
RESET
I
To enter the reset state, this pin must be kept L for more that 2
μ
s (20
Φ
cycles under normal V
cc
conditions). If
the crystal or ceramic resonator requires more time to stabilize, extend this L level time appropriately.
An external ceramic or quartz crystal oscillator can be connected between the XC
in
and XC
out
pins. If an
external clock source is used, connect the clock source to the XC
in
pin and leave the XC
out
pin open.
Input and output signals to and from the internal clock generation circuit. Connect a ceramic resonator or quartz
crystal between X
in
and X
out
pins to set the oscillation frequency. If an external clock is used, connect the clock
source to the X
in
pin and leave the X
out
pin open.
O Loop filter for the frequency synthesizer.
An external capacitor (Ext. Cap) pin. When the USB transceiver voltage converter is used, a 2
μ
f or larger
capacitor should connect between this pin and V
ss
to ensure proper operation of the USB line driver. The
voltage converter is enabled by setting bit 4 of the USB control register (0013
16
) to a “1”.
10
XC
in
XC
out
I
O
12
11
X
in
X
out
I
O
14
15
LPF
18
Ext. Cap
I
72
Table 1-2. Pin Description
Name
I/O
Description
Pin #
C1
C2
Pin 73
(
VSS
)
Pin 74
(
VDD
)
C1
C2
Pin 13
(
VSS
)
Pin 16
(
VDD
)
C1
C2
Pin 17
(A
VSS
)
Pin 19
(A
VDD
)
C1 = 4.7
μ
F
C2 = 0.1
μ
F
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