參數(shù)資料
型號: M37640E8
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
中文描述: 單芯片8位CMOS單片機(jī)
文件頁數(shù): 103/172頁
文件大小: 1193K
代理商: M37640E8
7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
UART
7/9/98
2-91
The UART generates the Transmit interrupt when either the Transmit Buffer Empty Flag (TBE) or the
Transmit Complete Flag (TCM) are set, depending on the state of the Transmit Interrupt Source
Selection Bit (TIS, bit 4 of UxCON). The UART generates the Receive Buffer Full interrupt when
receiving and the Receive Buffer Full Flag is set to a “1”. The Receive Error Sum interrupt is
generated instead of a Receive Buffer Full interrupt if the UART detects an error when receiving.
Enabling a transmit or receive operation by setting the TEN or the REN (bits 0 and 1 of UxCON)
automatically forces the corresponding UART port pins in the appropriate direction.
The UART supports an address mode for use in a multi-receiver environment where an address is sent
before each message to designate which UART or UARTs are to wake-up and receive the message.
Figure 2-108 is a block diagram of the UART. It is valid for both UART1 and UART2.
Figure 2-108. UART Block Diagram
2.14.1 Baud Rate Selection
UART rate selection is controlled by the UxBRG and is calculated as follows:
Baud Rate =
f
/
[16 x (
n
+ 1)]
where
n
denotes the decimal value set in the UxBRG, and where
f
denotes the clock frequency that
depends on the clock selection and the prescale value chosen.
Either an internal clock
Φ
or the output of the chip special count source generator (SCSGCLK) can be
selected as the input clock source by means of the UART Clock Selection Bit (CLK, bit 0 of the
UART Mode Register (UxMOD)). Bits PS0 and PS1 of the UxMOD are used to select a prescaling
factor for the clock.
When the internal clock
Φ
is selected,
f
is the prescaled value of the internal clock
Φ
.
f
=
Φ
/1,
Φ
/8,
Φ
/32, or
Φ
/256
URegister
UxMOD
URegister
UxCON
STransmit
Data Bus
TBuffer
URegister
UxSTS
Data Bus
ST/STP/PA
BReceive
StoDetect
Bit Counter
LE 1,0; PEN; STB
Bit Counter
/1/8/32/256
Clock Set
Tx Enable
Tx Buffer Empty
TBE
TIS = “0”
TIS = “1”
TCM
Transmit line to UTXDx
Receive line from URXDx
Receive Buffer Full Interrupt
Receive Error Interrupt
Rx Complete
Rx Status Errors
Tx Complete
LE 1,0; PEN; STB
PS 1,0
CLKSEL
Φ
SCSGCLK
Transmit Interrupt
Baud Rate Generator
Rx Enable
ShReceive
To RTSx
RRegister
From CTSx
RTS_SEL
CTS_SEL
Data Bus
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