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參數(shù)資料
| 型號(hào)： | M37640E8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER |
| 中文描述： | 單芯片8位CMOS單片機(jī) |
| 文件頁數(shù)： | 161/172頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | M37640E8 |
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7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
6/2/98
5-11
Figure 5-22. UxCON Register
Figure 5-23. UxRTSC Register
MSB
7
LSB
0
AME
TIS
RIN
REN
TEN
TEN
Transmission Enable Bit (bit 0)
0: Disable the transmit process
1: Enables the transmit process. If the transmit process is disabled (TEN cleared)
during transmission, the transmit will not stop until completed.
Receive Enable Bit (bit 1)
0: Disable the receive process
1: Enables the receive process. If the receive process is disabled (REN cleared)
during reception, the receive will not stop until completed.
Transmission Initialization Bit (bit 2)
0: No action.
1: Resets the UART transmit status register bits as well as stopping the transmission
operation. The TEN bit must be set and the transmit buffer reloaded in order to transmit
again. The TIN is automatically reset one cycle after TIN is set.
Receive Initialization Bit (bit 3)
0: No action.
1: Clears the UART receive status flags and the REN bit. If RIN is set during receive in
progress, receive operation is aborted. The RIN bit is automatically reset one cycle
after RIN is set.
Transmit Interrupt Source Selection Bit (bit 4)
0: Transmit interrupt occurs when the Transmit Buffer Empty flag is set.
1: Transmit interrupt occurs when the Transmit Complete flag is set.
Clear-to-Send (CTS) Enable Bit (bit 5)
0: CTS function is disabled, P8
6
(or P8
2
) is used as GPIO pin.
1: CTS function is enabled, P8
(or P8
2
) is used as CTS input.
Request-to-Send (RTS) Enable Bit (bit 6)
0: RTS function is disabled, P8
7
(or P8
3
) is used as GPIO pin.
1: RTS function is enabled, P8
(or P8
3
) is used as RTS output.
UART Address Mode Enable Bit (bit 7)
0: Address Mode disabled.
1: Address Mode enabled.
REN
TIN
RIN
TIS
CTS_SEL
RTS_SEL
AME
Access: R/W
Reset: 00
16
RTS_SEL
CTS_SEL
TIN
Address: 0033
16
,003B
16
MSB
7
LSB
0
RTS2
RTS1
RTS0
Bits 0-3
RTS3:0
Reserved (Read/Write “0”)
RTS Assertion Delay Count 3:0 (bits 7,6,5,4)
0000:
No delay, RTS asserts immediately after receive operation completes.
0001:
RTS asserts 8 bit-times after receive operation completes.
0010:
RTS asserts 16 bit-times after receive operation completes.
0011:
RTS asserts 24 bit-times after receive operation completes.
.
.
.
1000:
RTS asserts 64 bit-times after receive operation completes.
.
.
.
1110:
RTS asserts 112 bit-times after receive operation completes.
1111:
RTS asserts 120 bit-times after receive operation completes.
Access: R/W
Reset: 80
16
RTS3
Address: 0036
16
, 003E
16
Reserved
Reserved
Reserved
Reserved
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