參數(shù)資料
型號： M37640E8
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
中文描述： 單芯片8位CMOS單片機(jī)
文件頁數(shù)： 146/172頁
文件大?。?/td> 1193K
代理商： M37640E8
4-10
8/10/98
Using the Frequency Synthesizer and DC-DC Converter
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Example: A 2.3
μ
F capacitor connected to Ext Cap requires 3.3ms for the voltage on Ext Cap to be stable.
Enable the USB clock by setting USBC5 (bit 5 of USBC) to a "1". (If the USB clock and FCU
are enabled before the voltage on Ext Cap is stable, a phantom USB Reset may be detected, or
the actual USB Reset may not be detected.)
Wait at least 4 cycles of
Φ
, then enable the USB FCU by setting USBC7 (bit 7 of USBC) to a
"1".
Enable other blocks as necessary.
Figure 4-6. PLL and DC-DC Converter Set Up Timing after Hardware Reset
4.6.2.2
Set up after USB Reset Signaling Detected
A USB Reset is detected by the USB FCU when an SE0 is present on D+/D- for at least 2.5
μ
s.
Detection of a USB Reset results in bit 5 of USB Interrupt Status Register 2 (USBIS2) being set to a
“1” and the registers within the USB FCU being reset to their default values. Register USBC and the
PLL registers are not affected by a USB Reset. A USB Function Interrupt request is also generated
when the USB Reset is detected.
No modifications to the frequency synthesizer or DC-DC converter configuration should be made in the
USB Function Interrupt routine. However, all USB FCU registers (addresses 0050
16
to 005F
16
) must be
reconfigured to their pre-enumeration state.
4.6.2.3
Set up after USB Suspend Detected
A USB Suspend occurs if the USB FCU does not detect any bus activity on D+/D- for at least 3ms.
Detection of a suspend results in bit 7 of USBIS2 being set to a “1”. If bit 7 of the USB Interrupt
Enable Register 2 (USBIE2) is a “1”, a USB Function Interrupt request is also generated.
The configuration of the frequency synthesizer and DC-DC converter should be changed as follows in
the USB Function Interrupt routine (if the device is bus powered):
Disable the USB clock by setting USBC5 (bit 5 of USBC) to a "0".
Disable the PLL by setting FSE (bit 0 of FSC) to a "0".
RESET
FSE
LS
USBC4
USBC5
USBC7
Wait 2ms
Wait (C+1)ms
Enable PLL
Enable DC-DC converter
Enable USB Clock
Enable USB FCU
Wait at least 4 cycles of
Φ
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