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參數(shù)資料
| 型號： | M37640E8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER |
| 中文描述： | 單芯片8位CMOS單片機 |
| 文件頁數(shù)： | 139/172頁 |
| 文件大小： | 1193K |
| 代理商： | M37640E8 |
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7600 Series
Mitsubishi Microcomputer
4 Application Notes
M37640E8-XXXF Preliminary Specification
DMAC
8/10/98
4-3
4.1
DMAC
4.1.1
Application
The following is an example of how to set up the DMAC for interfacing with a peripheral block. In
this case data is being transferred by DMAC channel 0 from UART1 receive buffer to user RAM.
Write 08
16
to DMA0M1 so that after each transfer the destination register will be decremented by
one and the source register will remain unchanged.
Write 00
16
to the low-order byte of the destination register (DMA0DL) and 03
16
to the high-order
byte of the destination register (DMA0DH) so that the data received by the UART is placed in
page three of the user RAM starting from address 0300
16
.
Write 34
16
to the low-order byte of the source register (DMA0SL) and 00
16
to the high-order byte
of the source register (DMA0SH) so that the DMAC reads from address 0034
16
, which is the low-
order byte of the UART receive buffer.
Write to the transfer count register (DMA0CL/H) with a 16-bit value that corresponds to the
number of transfers to occur before flag CRUF and the DMAC channel 0 interrupt are set.
Set the DMAC transfer initiating source to the UART receive interrupt by writing 01
16
to
DMA0M2.
Place the UART in the desired configuration for data reception by writing to the UART control
(U1CON), UART mode (U1MOD), and UART baud rate (U1BRG) registers.
Disable the UART receive interrupt from being serviced by the CPU by setting to a "0" bit 6 of
interrupt control register A (ICONA).
Enable the DMAC channel 0 interrupt by setting bit 4 of ICONA to "1".
Enable DMAC channel 0 and reset the initiating source sample latch by writing C1
16
to DMA0M2.
The DMA controller will transfer one byte of data from the UART receive buffer to third page user
RAM each time that the UART1 receive interrupt is set. Because the destination register is incremented
by one after each transfer, third page user RAM is contiguously filled with received data.
The transfer count register decrements by one after each transfer. When it underflows, flag D0UF and
the DMAC channel 0 interrupt are set. In the DMAC channel 0 service routine, the user can either
write new values to the source, destination, and transfer count registers, or leave these registers
untouched. If they are left untouched, then they contain the previously written values that were
reloaded when the transfer count register underflowed. This would result in the previously transferred
UART data in third page user RAM being overwritten with newly received UART data.
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