參數(shù)資料
型號(hào)： M37640E8
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
中文描述： 單芯片8位CMOS單片機(jī)
文件頁數(shù)： 85/172頁
文件大小： 1193K
代理商： M37640E8
7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
Direct Memory Access Controller
7/9/98
2-73
In order for this mode to function correctly, the time from the DMAC writing data to MBI output
buffer x (which causes pin OBFx to go high) until the end of a master read of MBI output buffer
x) must be greater than 104.167*(3 - (12E6/
Φ
))ns. For example, if
Φ
= 12MHz, the delay must be
greater than 208.334ns, and if
Φ
= 6MHz, the delay must be greater than 104.167ns. When
Φ
is
less than or equal to 4MHz, no delay is required.
Byte-by-Byte Transfers
When the USB endpoint 1 OUT_FIFO_NOT_EMPTY signal is chosen as the hardware transfer
request source for a DMAC channel and the DxUMIE bit of the same channel is set to a “1”, a
transfer request is generated for the DMAC channel if the endpoint 1 OUT FIFO is not empty and
output buffer x of the MBI is empty. Thus, a transfer request is generated as soon as new data is
received in the endpoint 1 OUT FIFO and the master CPU has read the data previously placed in
MBI output buffer x. As is the case when the packet-by-packet method is used, the OUT_PKT_RDY
signal goes high once a complete packet has been received. It remains high until all bytes of the
packet have been read from the OUT FIFO. When the final byte has been read from the OUT
FIFO, the OUT_PKT_RDY signal goes low (if this option is enabled in the USB block), which
causes the source, destination, and transfer count registers of the involved DMAC channel to be
reloaded (unless the DRLDD bit is set to a “1”) and the DMAC interrupt corresponding to the
involved channel to be set. Also, if the DxDAUE bit associated with the channel is “1”, the
channel’s DxCEN bit is automatically cleared to “0”, disabling the channel. If the last byte of the
packet has been read from the OUT FIFO before the end_of_packet signal is received by the USB
block, the OUT_PKT_RDY signal will still go high and then low a short period of time later (if
this option is enabled in the USB block).
This feature allows a channel of the DMAC in single-byte transfer mode to automatically transfer
data received for endpoint 1 from the endpoint 1 OUT FIFO to the master CPU (via the MBI) prior
to reception of the complete packet.
MBI Input Buffer to USB IN FIFO Transfers
When a USB endpoint IN_PKT_RDY signal is selected as the hardware transfer request source for a
DMAC channel and the DxUMIE bit of the same channel is set to a “1”, a transfer request is
generated when the IN FIFO associated with the endpoint is not full (with respect to the
programmed packet size) and input buffer x of the MBI contains data. The transfer request is not
generated if input buffer x contains a command. The IN FIFO associated with an endpoint is not
full when IN_PKT_RDY is low. The IN_PKT_RDY signal remains low until a full packet has been
written to the IN FIFO. Thus, the first transfer request is generated when the IN_PKT_RDY goes
low and subsequent transfer requests are generated when data is written to input buffer x by an
external device. Once the full packet has been written to the IN FIFO, the IN_PKT_RDY signal is
automatically set to a “1” (assuming this option is enabled in the USB block). In this case, the
source, destination, and transfer count registers are not automatically reloaded. Instead, the packet
size for the endpoint should be written to the transfer count register at initialization time so that it
underflows and reloads the registers once the last byte of the data is transferred from input buffer x
to the endpoint’s IN FIFO.
The feature described above allows a channel of the DMAC, in single-byte transfer mode, to
automatically transfer data received from the master CPU (via the MBI) to the endpoint’s IN FIFO
without any intervention by the on-chip CPU. Additionally, since the IN_PKT_RDY signal associated
with the endpoint is automatically set (assuming this option is enabled in the USB block), multiple
packets can be transferred by a channel of the DMAC without on-chip CPU intervention. Note
however that short packets are not handled automatically and instead require intervention by the on-
chip CPU.
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