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參數(shù)資料
| 型號(hào)： | M37640E8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER |
| 中文描述： | 單芯片8位CMOS單片機(jī) |
| 文件頁數(shù)： | 73/172頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | M37640E8 |
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7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
Universal Serial Bus
7/9/98
2-61
INXCSR7
(AUTO_SET): If the CPU sets this bit to a “1”, the IN_PKT_RDY bit is set automatically
by the USB FCU after the number of bytes of data equal to the maximum packet size (MAXP) is
written into the IN FIFO (see Chapter 2.9.3.1. IN (Transmit) FIFOs for details).
Figure 2-75. USB Endpoints x IN CSR
All bits in
USB Endpoint 0 OUT CSR
(Control & Status Register), shown in Figure 2-76, are
reserved (all control and status info is in Endpoint 0 IN CSR)
Figure 2-76. USB Endpoint 0 OUT CSR
The
USB Endpoint x OUT CSR
(Control & Status Register), shown in Figure 2-77, contains control
and status information of the respective OUT endpoint 1-4. The specific endpoint is selected by the
USB Endpoint Index Register.
OUTXCSR0
(OUT_PKT_RDY): The USB FCU sets the this bit to a “1” after it successfully receives a
packet of data from the host. This bit is cleared by the CPU or by the USB FCU after a packet of data
is unloaded from the FIFO (See Chapter 2.9.3.2. Out (Receive) FIFOs for details).
OUTXCSR1
(OVER_RUN): This bit is used in ISO mode only to indicate to the CPU that a FIFO overrun
has occurred. The USB FCU sets this bit to a “1” at the beginning of an OUT token if the
OUTXCSR0 (OUT_PKT_RDY) bit is not cleared. Setting this bit will cause the INST12 bit of the
Interrupt Status Register 2 to set. The CPU writes a “0” to clear this bit.
OUTXCSR2
(SEND_STALL): The CPU writes a “1” to this bit when the endpoint is stalled (receiver
halt). The USB FCU returns a STALL handshake while this bit is set. The CPU writes a “0” to clear
this bit.
OUTXCSR3
(ISO): The CPU sets this bit to a “1” to initialize the respective endpoint as an Isochronous
endpoint for OUT transactions.
INXCSR0
IN_PKT_RDY Bit (bit 0) (Write “1” only or Read)
0: In packet is not ready
1: In packet is ready
UNDER_RUN Flag (bit 1) (Write “0” only or Read)
0: No FIFO underrun
1: FIFO underrun has occurred
SEND_STALL Bit (bit 2)
0: No action
1: Stall IN Endpoint X by the CPU
ISO Bit (bit 3)
0: Select non-isochronous transfer
1: Select isochronous transfer
INTPT Bit (bit 4)
0: Select non-rate feedback interrupt transfer
1: Select rate feedback interrupt transfer
TX_NOT_EPT Flag (bit 5) (Read Only - Write “0”)
0: Transmit FIFO is empty
1: Transmit FIFO is not empty
FLUSH Bit (bit 6) (Write Only - Read “0”)
0: No action
1: Flush the FIFO
AUTO_SET Bit (bit 7)
0: AUTO_SET disabled
1: AUTO_SET enabled
INXCSR1
INXCSR2
INXCSR3
INXCSR4
INXCSR5
INXCSR6
INXCSR7
MSB
7
LSB
0
INXCSR7
INXCSR6
INXCSR5
INXCSR4
INXCSR3
INXCSR1
INXCSR0
Access: R/W
Reset: 00
16
INXCSR2
Address: 0059
16
Bits 7:0
Reserved (Read “0”)
MSB
7
LSB
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Access: R
Reset: 00
16
Address: 005A
16
Reserved
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