參數(shù)資料
型號： M37640E8
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
中文描述： 單芯片8位CMOS單片機(jī)
文件頁數(shù)： 11/172頁
文件大?。?/td> 1193K
代理商： M37640E8
7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
Pin Description and Layout
6/2/98
1-7
Table 1-2. Pin Description
Name
I/O
I/Ofunction as the address bus.
I/Ofunction as the data bus. These pins may also be used to implement the Key-on Wake up function.
I/Oas RDY (hardware wait cycle control).
I/O CMOS I/O port.
P3
2
/(VRFY) I/Overify).
CMOS I/O port (DMA
out
). When the MCU is in memory expansion or microprocessor mode, this pin is set to a
“1” during a DMA transfer. When the MCU is in EPROM program mode, the pin is used as PGM (EPROM
memory program).
I/Opin.
Φ
). When the MCU is in memory expansion or microprocessor mode, this pin becomes
Φ
out
P3
5
/SYNC
out
I/Obecomes the SYNCout pin.
CMOS I/O port. (WR output). When the MCU is in memory expansion or microprocessor mode, this pin
becomes WR. When the MCU is in EPROM program mode, the pin is used as CE (EPROM memory chip
enable).
CMOS I/O port. (RD output). When the MCU is in memory expansion or microprocessor mode, this pin
becomes RD. When the MCU is in EPROM program mode, the pin is used as OE (EPROM memory output
enable).
I/Omicroprocessor mode, this pin can become the EDMA pin.
P4
1
/INT0
~ P4
2
/INT1
CMOS I/O port or Timer X input pin for pulse width measurement mode and event counter mode or Timer X
output pin for pulse output mode. This pin can also be used as an external interrupt when Timer X is not in
output mode. The interrupt polarity is selected in the Timer X mode register.
CMOS I/O port or Timer Y input pin for pulse period measurement mode, pulse H-L measurement mode and
event counter mode or Timer Y output pin for pulse output mode. This pin can also be used as an external
interrupt when Timer Y is not in output mode. The interrupt polarity is selected in the Timer Y mode register.
P5
0
/XC
in
I/O CMOS I/O port or XC
in
.
P5
1
/T
out
/
XC
out
P5
2
/OBF
0
I/O CMOS I/O port or OBF
0
output to master CPU for data bus buffer 0.
P5
3
/IBF
0
I/O CMOS I/O port or IBF
0
output to master CPU for data bus buffer 0.
P5
4
/S
0
I/O CMOS I/O port or S
0
input from master CPU for data bus buffer 0.
P5
5
/A
0
I/O CMOS I/O port or A
0
input from master CPU.
P5
6
/R(E)
I/O CMOS I/O port or R(E) input from master CPU.
P5
7
/W(R/W) I/O CMOS I/O port or W(R/W) input from master CPU.
P6
0
/DQ0
~ P6
7
/DQ7
USB D
-
I/O USB D- voltage line interface, a series resistor of 33
should be connected to this pin. (see note)
USB D
+
I/O USB D+ voltage line interface, a series resistor of 33
should be connected to this pin. (see note)
P7
0
/SOF
I/O CMOS I/O port or USB start of frame pulse output, an 80 ns pulse outputs on this pin for every USB frame.
P7
1
/HOLD
I/O CMOS I/O port or HOLD pin.
P7
2
/S
1
I/O CMOS I/O port or S
1
input from master CPU for data bus buffer 1.
Description
Pin #
P0
0
/AB0
~ P1
7
/AB15
P2
0
/DB0
~ P2
7
/DB7
56-41
64-57
P3
0
/RDY
40
P3
1
39
38
P3
3
/DMA
out
/PGM
I/O
37
P3
4
/
Φ
out
36
35
P3
6
/WR/(CE) I/O
34
P3
7
/RD/(OE) I/O
33
P4
0
/EDMA
24
I/Oactive high or low.
23-22
P4
3
/CNTR0
I/O
21
P4
4
/CNTR1
I/O
20
12
I/O CMOS I/O port or Timer 1/2 pulse output pin (can be configured initially high or initially low), or XC
out
.
11
8
7
6
5
4
3
I/O CMOS I/O port or master CPU data bus.
2-1,
80-75
71
70
69
68
67
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