參數(shù)資料
型號(hào): M37640E8
廠(chǎng)商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
中文描述: 單芯片8位CMOS單片機(jī)
文件頁(yè)數(shù): 86/172頁(yè)
文件大?。?/td> 1193K
代理商: M37640E8
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2-74
7/9/98
Direct Memory Access Controller
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
2.11.1.4
DMAC Transfer Mode
Each channel of the DMAC can be operated in single-byte transfer mode or burst transfer mode. The
choice is made by the setting of the Channel x DMAC Transfer Mode Selection Bit (DxTMS). When
single-byte transfer mode is selected, one byte of data is transferred per transfer request. When burst
transfer mode is selected, the value in the transfer count register determines how many single byte
transfers occur per transfer request. For example, if the value in the transfer count register is 0014
16
,
21 transfers will occur before control of the address bus and data bus is given back to the CPU.
2.11.1.5
DMAC Transfer Timing
A DMAC transfer can occur at any point during the execution of an instruction by the CPU. However, at
least one cycle of
Φ
with the CPU operating takes place between transfers by the same DMAC channel
caused by different events or between transfers by the two DMAC channels. Also, burst transfers and
possibly single-byte transfers are prevented from occurring during interrupt service routines.
The transfer initiating sources for the two channels are latched by the DMAC asynchronously and
polled on the rising edge of
Φ
. If a transfer request is seen for both channels, the channel 0 request
will be serviced first followed by the channel 1 request.
If channel 1 is performing a burst transfer when channel 0 receives a transfer request, the channel 1
transfer is suspended at the end of the next source read/destination write operation. The channel 0
transfer is then serviced. Once the channel 0 transfer completes, the channel 1 transfer automatically
continues where it left off. In order to prevent channel 0 from completely shutting out channel 1
transfers, one cycle of a suspended channel 1 transfer is allowed to occur after a channel 0 burst
transfer even if another channel 0 transfer request is pending.
If the I flag value is “0” and an interrupt with its interrupt control bit set to a “1” occurs during a
burst transfer by either channel, the transfer is suspended, allowing the interrupt service routine to be
entered. The DMAC Channel x Suspend (due to interrupt service request) Flag (DxSFI) corresponding
to the channel whose transfer was suspended is automatically set to a “1” at this time. When the I
flag value (which was automatically set to a “1” when the interrupt service routine was entered)
becomes a “0” again, the DxSF flag is automatically cleared and the transfer continues where it left
off. If a DMAC burst transfer request occurs during the servicing of an interrupt, the transfer does not
take place until after the interrupt has been serviced, which is understood to have happened when the I
flag becomes a “0”.
If the DMAC Transfer Suspend Control Bit (DTSC) is set to a “1”, both single-byte and burst mode
transfers are suspended by interrupts.
A suspended DMAC transfer can be re-started in the interrupt service routine by writing a “1” to the
DxCEN bit of the suspended channel.
Sample timing diagrams are shown in Figure 2-98, Figure 2-99, and Figure 2-100. for a single-byte
transfer initiated by a hardware source, a single-byte transfer initiated by the software trigger, and a
burst transfer initiated by a hardware source, respectively.
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