
2-96
7/9/98
UART
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
Figure 2-111. UxSTS Register
2.14.6 Transmit/Receive Format
Transmit Method
(See Figure 2-112.)
Setup
Define the baud rate by writing a value from 0-255 into the UxBRG.
Set the Transmission Initialization Bit (TIN, bit 2 of UxCON), to “1”. This will reset the transmit
status to a value of 03
16.
Select the interrupt source to be either TBE or TCM by clearing or setting the Transmit Interrupt
Source Selection Bit (TIS, bit 4 of UxCON).
Configure the data format and clock selection by writing the appropriate value to UxMOD.
Set the Clear-To-Send Enable Bit (CTS_SEL, bit 5 of UxCON), if CTS handshaking will be
used.
Set the Transmit Enable Bit (TEN, bit 0 of UxCON), to “1”.
Operation
When data is written to the low-order byte of the transmit buffer (UxTRB1), TBE is cleared to
“0”. If 9-bit character length has been selected, the high-order byte of the transmit buffer
(UxTRB2) should be written before the low-order byte (UxTRB1).
If no data is being shifted out of the transmit shift register and CTS handshaking is disabled, the
data written to the transmit buffer is transferred to the transmit shift register and the TCM flag in
UxSTS is cleared to a “0”. In addition, the TBE flag is set to a “1”, signalling that the next byte
of data can be written to the transmit buffer. If CTS handshaking is enabled, the operation
described above does not take place until CTSx is brought low.
Data from the transmit shift register is transmitted one bit at a time beginning with the start bit
and ending with the stop bit. Note that the LSB is transmitted first.
If the TEN bit is cleared to a “0” while data is still being transmitted, the transmitter will con-
tinue until the last bit is sent. This is also the case when CTS handshaking is enabled and CTSx
is brought back high during transmission.
MSB
7
LSB
0
SER
OER
FER
PER
TBE
TCM
TCM
Transmit-Complete (Transmission Register Empty) Flag (bit 0)
0: Data in the transmission register.
1: No data in the transmission register.
TX Buffer Empty Flag (bit 1)
0: Data in the TX Buffer.
1: No data in the TX Buffer.
RX Buffer Full Flag (bit 2)
0: No data in the RX Buffer.
1: Data in the RX Buffer.
Receive Parity Error Flag (bit 3)
0: No receive parity error.
1: Receive parity error.
Receive Framing Error Flag (bit 4)
0: No receive framing error.
1: Receive framing error.
Receive Overrun Flag (bit 5)
0: No receive overrun.
1: Receive overrun.
Receive Error Sum Flag (bit 6)
0: No receive error.
1: Receive error.
Reserved (Read “0”)
TBE
RBF
PER
FER
OER
SER
Bit 7
Access: R only
Reset: 03
16
RBF
Address: 0032
16
, 003A
16
Reserved