參數(shù)資料
型號： M37640E8
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCONTROLLER
中文描述： 單芯片8位CMOS單片機
文件頁數(shù)： 94/172頁
文件大?。?/td> 1193K
代理商： M37640E8
2-82
7/9/98
Timers
7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
2.13 Timers
This device has five built-in timers: Timer X, Timer Y, Timer 1, Timer 2, and Timer 3.
The contents of the timer latch, corresponding to each timer, determine the divide ratio. The timers can
be read or written at any time. However, the read and write operations on the high and low-order
bytes of the 16-bit timers (Timer X and Y) must be performed in a specific order.
The timers are all down count timers; when the count of a timer reaches 00
16
(0000
16
for Timer X
and Y), an underflow occurs at the next count pulse and the contents of the corresponding timer reload
latch are reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to
that timer is set to a “1”.
The divide ratio of a timer is given by 1/(
n
+ 1), where
n
is the value written to the timer. When the
STP instruction is executed or RESET is asserted, 01
16
is loaded into Timer 2 and the Timer 2 reload
latch, and FF
16
is loaded into Timer 1 and the Timer 1 reload latch.
Figure 2-107. is a block diagram of the five timers.
2.13.1 Timer X
Timer X is a 16-bit timer that has a 16-bit reload latch, and can be placed in one of four modes by
setting bits TXM4 and TXM5 (bits 4 and 5 of the Mode Register, TXM). The bit assignment of the
TXM is shown in Figure 2-104.
2.13.1.1
Read and Write Method
Read and write operations on the high and low-order bytes of Timer X must be performed in a
specific order.
Write Method
When writing to the timer, the lower order byte is written first. This data is placed in a temporary register
that is assigned the same address as Timer XL. Next, the higher order byte is written. When this is done,
the data is placed in the Timer XH reload latch and the low-order byte is transferred from its temporary
register to the Timer XL reload latch. At this point, if the Timer X Data Write Control Bit (TXM0) (bit 0)
is “0”, the value in the Timer X reload latch is also loaded in Timer X. If TXM0 is “1”, the data in the
Timer X reload latch is loaded in Timer X after Timer X underflows.
Address
Description
Acronym and
Value at Reset
Address
Description
Acronym and
Value at Reset
0020
16
0021
16
0022
16
0023
16
0024
16
Timer XL
Timer XH
Timer YL
Timer YH
Timer 1
TXL=FF
TXH=FF
TYL=FF
TYH=FF
T1=FF
0025
16
0026
16
0027
16
0028
16
0029
16
Timer 2
Timer 3
Timer X mode register
Timer Y mode register
Timer 123 mode register T123M=00
T2=01
T3=FF
TXM=00
TYM=00
Bit5 -TXM5
Bit4 -TXM4
Timer X Mode
0
0
1
1
0
1
0
1
Timer mode
Pulse output mode
Event counter mode
Pulse width measurement mode
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