
7600 Series
Mitsubishi Microcomputer
M37640E8-XXXF Preliminary Specification
Interrupt Control Unit
7/9/98
2-43
2.8
Interrupt Control Unit
The interrupt control unit (ICU), a specialized peripheral, is described in detail in this section.
This series supports a maximum of 23 maskable interrupts, one software interrupt, and one reset
vector that is treated as a non-maskable interrupt.
See Table 2-3 for the interrupt sources, jump destination addresses, interrupt priorities, and section
references for the interrupt request sources.
2.8.1
Interrupt Control
Each maskable interrupt has associated with it an interrupt request bit and an interrupt enable bit.
These bits, along with the I flag, determine whether interrupt events can cause an interrupt service
request to be generated. An interrupt request bit is set to at “1” when its corresponding interrupt
event is activated. The bit is cleared to a “0” when the interrupt is serviced or when a “0” is written
to the bit. The bit can not be set high by writing “1” to it.
Each interrupt enable bit determines whether the interrupt request bit it is paired with is seen when the
interrupts are polled. When the interrupt enable bit is a “0”, the interrupt request bit is not seen; and
when the enable bit is a “1”, the interrupt request is seen.
The interrupt request register configurations for the 23 maskable interrupts are shown in Figure 2-52.,
Figure 2-53., and Figure 2-54. The interrupt control register configurations for the 23 maskable
interrupts are shown in Figure 2-55., Figure 2-56., and Figure 2-57.
Figure 2-52. IREQA Configuration
Address
Description
Acronym and
Value at Reset
Address
Description
Acronym and
Value at Reset
0002
16
0003
16
0004
16
0005
16
Interrupt request register A
Interrupt request register B
Interrupt request register C
Interrupt control register A
IREQA=00
IREQB=00
IREQC=00
ICONA=00
0006
16
0007
16
0011
16
Interrupt control register B
Interrupt control register C
Interrupt polarity selection register
ICONB=00
ICONC=00
IPOL=00
IRA0
IRA1
IRA2
IRA3
IRA4
IRA5
IRA6
IRA7
USB Function Interrupt Request (bit 0)
USB SOF Interrupt Request (bit 1)
External Interrupt 0 Request (bit 2)
External Interrupt 1 Request (bit 3)
DMAC channel 0 Interrupt Request (bit 4)
DMAC channel 1 Interrupt Request (bit 5)
UART1 Receive Buffer Full Interrupt Request (bit 6)
UART1 Transmit Interrupt Request (bit 7)
0: No interrupt request issued
1: Interrupt request issued
MSB
7
LSB
0
IRA7
IRA6
IRA5
IRA4
IRA3
IRA2
IRA1
IRA0
Access: R/W
Reset: 00
16
Address: 0002
16