參數(shù)資料
型號: L84302
元件分類: 通用總線功能
英文描述: L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述: L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊,4月2日
文件頁數(shù): 90/128頁
文件大?。?/td> 997K
代理商: L84302
90 of 128
April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
Bit 0 occurs on CDST0/CDST8 pin
Table 36
Counter 1-51 Register Definition
15
C15
R/W
14
C14
R/W
13
C13
R/W
12
C12
R/W
11
C11
R/W
10
C10
R/W
9
8
C9
R/W
C8
R/W
7
6
5
4
3
2
1
0
C7
R/W
C6
R/W
C5
R/W
C4
R/W
C3
R/W
C2
R/W
C1
R/W
C0
R/W
Bit
Symbol
Name
Definition
R/W
Def.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
Counter
These fifty-one registers contain the contents
of the fifty-one 32-bit management counters.
Each register corresponds to a one specific
counter. The register address and definition for
each counter is shown in
Table 12
.
The entire 32-bit word is obtained by doing two
consecutive read operations from the same
register address. The upper 16-bit word is out-
putted on the first read, the lower 16-bit word
on the second read. C0 of the lower 16-bit
word is the counter LSB.
R/W
0
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