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參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 47/128頁 |
| 文件大小： | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
47 of 128
April, 2002
3.11.6 10 Mbps Serial Interface
The 10 Mbps Serial Interface uses only seven pins in contrast to the
15-pin MII. The 10 Mbps Serial Interface only operates at 10 Mbps. The
10 Mbps serial mode is selected by setting the PHY interface select bit
in TX command register. The 10 Mbps Serial Interface is identical to the
MII at 10 Mbps except: (1) TXC and RXC frequency is 10 MHz instead
of 2.5 MHz, (2) Data is serial wide using only data pins RXD0 and TXD0
instead of nibble wide, (3) RXDV is not used, (4) RXER is not used, and
(5) the transmit data signals are referenced to TXC falling edge instead
of rising edge.
3.11.7 Clock Frequency Sense
As stated earlier, TXC must be continuously input at a frequency of 25
MHz in 100 Mbps mode and 2.5 MHz in 10 Mbps mode. The TXC
frequency is monitored by an internal clock frequency sense circuit and
the detected TXC frequency is stored in the TXC frequency detect bit in
the Miscellaneous Status register.
3.11.8 SQE
SQE (short for Signal Quality Error) is a pulse outputted on the COL pin
by an external PHY after the reception of each receive packet. SQE is
only enabled in 10 Mbps Serial mode. The detection of SQE pulses by
the L84302 is reported on the SQE detect bit in the Miscellaneous Status
register.
3.12 Management Interface (MI)
3.12.1 General
The Management Interface, referred to as the MI, is a serial interface for
passing data between an internal register and an external PHY. The MI
meets all IEEE 802.3 Clause 22 requirements.
The MI consists of two signals: one MI clock output (MDC), and one
bidirectional data line (MDIO).
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