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參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 27/128頁 |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
27 of 128
April, 2002
In addition to the RXRDY output, there is also a FIFO space/data
available output indication on the SPDTAVL pin. During a read operation,
the SPDTAVL output is a data available (almost empty) indication for the
receive FIFO and it is asserted active high if there is more than 1 double
words of data present in the receive FIFO.
RXDC_[1:4] is a receive packet discard output, one per port. RXDC_[1:4]
is asserted when an error was detected for a receive packet. When a
receive error is detected on a packet, the remaining contents of the RX
FIFO are flushed and RXDC_[1:4] is latched active high to indicate the
error condition. RXDC_[1:4] for the selected port can be cleared by
asserting the clearing signal, CLRRXERR. While RXDC_[1:4] is latched
high, the RX FIFO input is blocked and no data can be loaded into it until
it is cleared with CLRRXERR and the start of a new packet is detected.
See
Section 3.9, “Packet Discard,” page 41
, for more details on discards
and RXDC_[1:4].
The RXABORT input, when asserted, will discard the contents of the
receive FIFO, and halt the reception of any more data into the receive
FIFO until the start of the next packet is detected. Refer to
Section 3.9,
“Packet Discard,” page 41
, for more information about discarded packets.
The device can be programmed to disable and ignore the RXABORT pin
by setting the RXABORT pin disable bit in the Configuration 2 register.
A status word can be appended to the end of the receive packet, if
desired. Refer to
Section 3.10, “Receive Status Word,” page 43
, for more
details on the status word. The status word is always output on the next
full 32-bit word boundary after the data packet has ended, as shown in
Figure 4
.
3.4 Transmit MAC
3.4.1 General
The transmit MAC (Media Access Control) section receives data from the
transmit FIFO and generates an Ethernet MAC frame from this transmit
FIFO data by (1) generating preamble & SFD, (2) padding undersize
packet with 0’s to meet minimum packet size requirements, (3)
calculating and appending CRC value, and (4) maintaining the required
minimum interpacket gap to meet the defer requirements. In addition, the
transmit MAC will also retransmit data in case of a collision. Each of the
above operations can be individually disabled and modified, if desired.
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