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參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網的遠程監(jiān)控控制器/ SNMP管理處的技術手冊，4月2日 |
| 文件頁數(shù)： | 50/128頁 |
| 文件大小： | 997K |
| 代理商： | L84302 |
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April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
Command/Status 1 register is set to indicate that the operation is
complete. The interrupt pin is asserted after a read operation has
completed if the interrupt bit is set in the MI Command/Status 1 register.
After the completion of a read operation, the MDC clock is turned off and
MDIO is held high.
3.12.6 MDC Cycle Time
The MDC clock period is programmable and is a function of (1) the
system clock period, SLCK, and (2) the clock period select bits in the MI
Command/Status 0 register according to the equation shown in the MI
Command/ Status 0 register definition table (
Table 30
).
3.13 Full Duplex
3.13.1 General
Half-Duplex mode is the normal CSMA/CD operation defined in IEEE
802.3. Full Duplex mode allows transmission and reception to occur
simultaneously. When the device is placed in Full Duplex mode, the
collision function is disabled and the loopback of transmit to receive
(TXEN to CRS) caused by the external Physical Layer device must be
ignored.
3.13.2 Enabling Full Duplex
The device can be placed in Full Duplex mode, on a per port basis, by
either setting the FDUPLX_[1:4] pin for that port to Full Duplex mode or
by setting the Full Duplex select bit in the Configuration 1 register for that
port to Full Duplex mode. The interaction of the pin and bit is described
in
Table 10
. Note that both the pin and bit must be set to Half Duplex for
Half Duplex mode to be selected (i.e., 1 = Full Duplex; 0 = Half Duplex).
Table 10
FDX Bit and FDUPLX Pin Logic
FDX Bit in Config. 1 Reg.
FDUPLX Pin
1
1
0
0
1
0
1
0
Full Duplex
Full Duplex
Half Duplex
Full Duplex
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