參數資料
型號: L84302
元件分類: 通用總線功能
英文描述: L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述: L84302四100/10 Mbps的4端口以太網的遠程監(jiān)控控制器/ SNMP管理處的技術手冊,4月2日
文件頁數: 117/128頁
文件大?。?/td> 997K
代理商: L84302
Revision History
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
117 of 128
April, 2002
page 65
:
Section 3.19.2, “Timing”
, Paragraph 2 has been changed.
page 72
through
page 91
: Bit order for all tables has been reversed.
page 74
:
Table 18
, Definition copy change to bits 5, 6.
page 78
:
Table 23
, Definition copy change to bits 6, 2.
page 79
:
Table 24
, Definition copy change to bits 1, 2.
page 81
:
Table 26
, Definition copy change to bits 4, 5, 6, 7.
page 91
:
Table 37
, bits 3 thru 7, R/W and Def. are now blank.
page 92
:
Figure 8
has been changed
page 104
:
Figure 11
has been changed
page 110
:
Section 5.11, “Register Interface Timing Characteristics”
Sym t
97
, (Min) is now blank and (Max) has been changed to 4 SLCK
+ 50 ns
Sym t
98
, (Min) is now blank and (Max) has been changed to 3 SLCK
+ 50 ns
Sym t
99
, Parameter has been changed.
Sym t
100
, Parameter has been changed.
page 111
:
Figure 16
, “Ready” timing wave has been changed.
page 112
:
Figure 17
, has been changed.
page 114
: New Reset Timing table and
Figure 19
have been added.
page 121
: Appendix A is new.
6/24/99
Document Revision changed to MD400171/C
page 5
:
Section 1, “Pin Description”
Pins 134, 142, 150, 158: Copy changes to Description.
page 7
:
Section 1, “Pin Description”
Pin #68: Copy changes to Description.
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