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| 型號(hào)： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊(cè)，4月2日 |
| 文件頁(yè)數(shù)： | 39/128頁(yè) |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
39 of 128
April, 2002
3.7 Receive FIFO
3.7.1 General
The receive FIFO acts as a temporary buffer between the receive MAC
section and System Interface. The receive FIFO size is 128 bytes. Data
is clocked into the receive FIFO with the PHY Interface TXC clock. Data
is clocked out of the receive FIFO with the System Interface clock, SCLK.
There is one programmable watermark output and one almost full output
which aid in managing the data flow out of the receive FIFO.
3.7.2 Watermarks
There is one watermark for the receive FIFO. This watermark is output
on the RXRDY pin. This watermark is asserted when the receive FIFO
data exceeds or equals the thresholds associated with the watermark.
The receive watermark threshold for RXRDY and can be programmed
over the entire 128 byte receive FIFO range. The watermark threshold
can be programmed with four bits that reside in the FIFO Threshold
register. Once the data in the FIFO exceeds or equals the threshold of
the watermark, then the watermark pin on RXRDY is asserted active
high. RXRDY is also asserted if a complete packet is loaded into the
receive FIFO from the MII. The watermark stays asserted until the data
in the FIFO goes below the programmable threshold.
3.7.3 Almost Empty Indication
There is an almost empty output indication for the receive FIFO on the
SPDTAVL pin. When a RX FIFO read operation is in progress, the
SPDTAVL output pin will be asserted active low if there is less than three
double words of data in the receive FIFO.
3.7.4 RX Overflow
The receive FIFO overflow condition occurs when the receive RX FIFO
is full and additional data is still being written into it from the MAC. If the
receive FIFO overflows, then (1) RXDC is asserted and latched, (2) all
data in the RX FIFO is discarded, (3) all input data to the RX FIFO is
blocked until the RXDC signal is cleared with CLRRXERR, (4) the RX
FIFO overflow bit is set as an indication of this condition in the RX Status
register, and (5) the interrupt pin is asserted for that port provided the
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