參數(shù)資料
型號: L84302
元件分類: 通用總線功能
英文描述: L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述: L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊,4月2日
文件頁數(shù): 83/128頁
文件大?。?/td> 997K
代理商: L84302
Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
83 of 128
April, 2002
Bit 0 occurs on CDST0/CDST8 pin
Table 28
Flow Control Pause Time 0-1 Register Definition
7
6
5
4
3
2
1
0
P7
R/W
P6
R/W
P5
R/W
P4
R/W
P3
R/W
P2
R/W
P1
R/W
P0
R/W
Bit
Symbol
Name
Definition
R/W
Def.
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
Pause Time
These two registers contain the 16-bit word
that is inserted into the pause_time parameter
field of all autogenerated transmit MAC Control
Pause frames. Upon successful reception of
these autogenerated Pause frames, a remote
device will not transmit data for a time interval
equal to the decimal value of this register times
512 bit times (100 Mbps bit time=10ns, 10
Mbps bit time=100ns)
Bit 0 of Register 0 corresponds to the LSB of
the pause_time parameter. Bit 7 of Register 1
corresponds to the MSB of the pause_time
parameter. The MSByte and LSBit of the
pause_time parameter is transmitted first, as
shown in
Figure 7
.
A value of 32
H
is internally added to this word.
Any pause_time Value <=32
H
will be sent as
32
H
.
R/W
0
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