參數(shù)資料
型號: L84302
元件分類: 通用總線功能
英文描述: L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述: L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術手冊,4月2日
文件頁數(shù): 81/128頁
文件大小: 997K
代理商: L84302
Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
81 of 128
April, 2002
Bit 0 occurs on CDST0/CDST8 pin
Table 26
Configuration 5 Register Definition
7
0
6
0
5
0
4
0
3
2
1
0
MAXPKT3
R/W
MAXPKT2
R/W
MAXPKT1
R/W
MXPKT0
R/W
R/W
R/W
R/W
R/W
Bit
Symbol
Name
Definition
R/W
Def.
7
6
5
4
Reserved, must always remain at default or
written to 0 for proper operation
R/W
0
3
2
1
0
MAXPKT3
MAXPKT2
MAXPKT1
MAXPKT0
Maximum Packet
Size Select
These bits determine the maximum packet
size for the MAC. These bits also determine
maximum packet size for counters if bit 7 in
Configuration 4 register is set to 1.
1111 = 1533 bytes
1110 = 1532 bytes
.
.
.
.
.
.
0010 = 1520 bytes
0001 = 1519 bytes
0000 = 1518 bytes
R/W
0
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