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參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 33/128頁 |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
33 of 128
April, 2002
function computes the CRC on the incoming DA and produces a 6-bit
number that is compared against the 64 values stored in the eight Hash
Filter 0-7 Registers. When the multicast packet destination address
passes the address filter, the packet is deemed valid and passed to the
receive FIFO; otherwise, the packet is rejected.
The multicast address filter requires 64 address filter bits to be written
into the Hash Filter 0-7 Registers. The multicast address-filtering
algorithm is as follows:
1.
Compute a separate 32-bit CRC on the destination address field
using the same IEEE 802.3 defined method that computes the
transmit CRC.
2.
Use bits 0-3 of the destination address FCS to select one of the
bytes in the 64-bit address filter, as shown in
Table 5
.
3.
Use bits 4-6 of the destination address FCS to select one of the bits
within the byte selected in (2) as shown in
Table 5
.
4.
If the bit selected in (3) is a “1”, the destination address passes the
filter; otherwise, the address fails the filter and the packet is rejected
and discarded.
Note that if all 64-bits of the address filter are programmed to all 1’s, then
the address filter passes all multicast addresses.
The Hash filter function is normally disabled. It can be enabled by setting
the receive hash filter enable bit in the Configuration 2 register.
The device can be programmed to reject all multicast packets, regardless
of their address, by appropriately setting the receive address match
select bits in the RX Command register.
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