參數(shù)資料
型號: L84302
元件分類: 通用總線功能
英文描述: L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述: L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊,4月2日
文件頁數(shù): 87/128頁
文件大?。?/td> 997K
代理商: L84302
Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
87 of 128
April, 2002
Bit 0 occurs on CDST0/CDST8 pin
Table 33
Counter Status 1-7 Register Definition
7
6
5
4
3
2
1
0
CSTS7
R/LHI
CSTS6
R/LHI
CSTS5
R/LHI
CSTS4
R/LHI
CSTS3
R/LHI
CSTS2
R/LHI
CSTS1
R/LHI
CSTS0
R/LHI
Bit
Symbol
Name
Definition
R/W
Def.
7
6
5
4
3
2
1
0
CSTS7
CSTS6
CSTS5
CSTS4
CSTS3
CSTS2
CSTS1
CSTS0
Counter Status
These seven registers contain 51 counter
status bits. The counter status bits indicate
when a counter is half full. Each bit corre-
sponds to one of the 51 counters. Bit 0 of
Register 1 corresponds to Counter 1 as
defined in
Table 15
; bit 2 of Register 7 cor-
responds to Counter 51.
1 = Counter has reached a count of
80000000
H
, i.e. half full.
0 = Count < 80000000
H
.
R/LHI
0
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