- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367493 > L84302 L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 PDF資料下載
參數(shù)資料
| 型號(hào)： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊(cè)，4月2日 |
| 文件頁(yè)數(shù)： | 25/128頁(yè) |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)當(dāng)前第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)
Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
25 of 128
April, 2002
3.3.5 Receive Read Operation
All receive and transmit data is clocked in/out on rising edges of the
system clock, SCLK. The SCLK input needs to be continuously input to
the device at a frequency between 25-50 MHz.
The System Interface is bidirectional. When it is configured for a receive
read operation, data that is stored in the receive FIFO is output to the
System Interface. A receive read operation is initiated by asserting
RXINTEN and RXRDEN. RXINTEN acts as a general receive enable
input, and asserting RXINTEN also activates the output drivers for the
RXRDY and RXDC pins and removes them from high impedance state.
Coincident or after RXINTEN is asserted, RXRDEN must be asserted to
actually start the read operation. If RXRDEN is then asserted while
RXINTEN is asserted, the oldest data word in the receive FIFO is
clocked out onto the RXTXDATA[31:0] I/O pins on each rising edge of the
SCLK clock for the port selected by the RXTXPS[1:0] inputs. RXINTEN
and RXRDEN can be continuously asserted and deasserted as many
times as desired while a packet is being written into the device. The last
word of the packet is indicated by the assertion of RXTXEOF on the
same SCLK rising edge that clocks out the last word of the packet. Once
the entire packet has been clocked out, then no more data is clocked out
on RXTXDATA[31:0] for 8 SCLK cycles, thus allowing extra dribble SCLK
clock cycles to occur after the end of packet, up to a maximum of 8
SCLKs. After 8 extra dribble SCLKs without a RXRDEN deassertion, the
next packet will be read out of the receive FIFO. If there is no packet in
FIFO after 8 extra dribble SCLKs, then invalid data will be read out.
RXTXDATA[31:0] input data is 32-bit-wide packet data whose format and
relationship to the MAC packet and PHY Interface is described in
Figure 4
.
The byte enable pins, RXTXBE[3:0], are used for both transmit and
receive operation, and they determine which bytes of the 32-bit
RXTXDATA[31:0] data word contain valid data. RXTXBE[3:0] can be
configured as either inputs or outputs during a receive read operation by
appropriately setting the byte enable direction bit in the Configuration 3
register. When they are configured as outputs, RXTXBE[3:0] are clocked
out on rising edges of SCLK along with each data word and indicate
which bytes of the 32-bit RXTXDATA[31:0] data word contain valid data.
Note that RXTXBE[3:0]=0000 for all words of the packet except the last
word; the last word of the packet may end on any one of the four byte
boundaries of the 32-bit data word. When they are configured as inputs,
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| L8560 | Low-Power SLIC with Ringing |
| L8567 | SLIC for Peoples Republic of China Applications |
| L8567-32PLCC | Telecommunication IC |
| L8567-44PLCC | Telecommunication IC |
| L8574D | CAP 15PF 50V 5% C0G SMD-0402 TR-7-PA SN100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L8446-04 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-06 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-07 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-41 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-42 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。