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參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 25/128頁 |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
25 of 128
April, 2002
3.3.5 Receive Read Operation
All receive and transmit data is clocked in/out on rising edges of the
system clock, SCLK. The SCLK input needs to be continuously input to
the device at a frequency between 25-50 MHz.
The System Interface is bidirectional. When it is configured for a receive
read operation, data that is stored in the receive FIFO is output to the
System Interface. A receive read operation is initiated by asserting
RXINTEN and RXRDEN. RXINTEN acts as a general receive enable
input, and asserting RXINTEN also activates the output drivers for the
RXRDY and RXDC pins and removes them from high impedance state.
Coincident or after RXINTEN is asserted, RXRDEN must be asserted to
actually start the read operation. If RXRDEN is then asserted while
RXINTEN is asserted, the oldest data word in the receive FIFO is
clocked out onto the RXTXDATA[31:0] I/O pins on each rising edge of the
SCLK clock for the port selected by the RXTXPS[1:0] inputs. RXINTEN
and RXRDEN can be continuously asserted and deasserted as many
times as desired while a packet is being written into the device. The last
word of the packet is indicated by the assertion of RXTXEOF on the
same SCLK rising edge that clocks out the last word of the packet. Once
the entire packet has been clocked out, then no more data is clocked out
on RXTXDATA[31:0] for 8 SCLK cycles, thus allowing extra dribble SCLK
clock cycles to occur after the end of packet, up to a maximum of 8
SCLKs. After 8 extra dribble SCLKs without a RXRDEN deassertion, the
next packet will be read out of the receive FIFO. If there is no packet in
FIFO after 8 extra dribble SCLKs, then invalid data will be read out.
RXTXDATA[31:0] input data is 32-bit-wide packet data whose format and
relationship to the MAC packet and PHY Interface is described in
Figure 4
.
The byte enable pins, RXTXBE[3:0], are used for both transmit and
receive operation, and they determine which bytes of the 32-bit
RXTXDATA[31:0] data word contain valid data. RXTXBE[3:0] can be
configured as either inputs or outputs during a receive read operation by
appropriately setting the byte enable direction bit in the Configuration 3
register. When they are configured as outputs, RXTXBE[3:0] are clocked
out on rising edges of SCLK along with each data word and indicate
which bytes of the 32-bit RXTXDATA[31:0] data word contain valid data.
Note that RXTXBE[3:0]=0000 for all words of the packet except the last
word; the last word of the packet may end on any one of the four byte
boundaries of the 32-bit data word. When they are configured as inputs,
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