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| 型號(hào)： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊(cè)，4月2日 |
| 文件頁(yè)數(shù)： | 49/128頁(yè) |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
49 of 128
April, 2002
An MI data transfer cycle consists of 64 bits: (1) The first 32 bits are the
idle pattern, (2) the next 16 bits are always written from the device to an
external PHY and contain command information related to the MI data
transfer cycle, and (3) the last 16 bits contain the actual data transferred
over the MI. The last 16 bits are output from the device when a write
cycle is selected and are input to the device when a read cycle is
selected.
3.12.3 Bit Definition
Table 9
defines the bits that comprise an MI data transfer cycle. Some
bits are read from/written to specific register bits. Other MI data transfer
cycle bits are generated by internal logic.
Table 9
lists the source of each
MI data transfer bit. Note that the registers are replicated per port; thus,
the values used on any particular MI data transfer cycle are obtained
from the MI registers of the selected port.
3.12.4 Write Operation
A write operation is defined as an MI data transfer cycle where the last
16 bits of data in the frame are obtained from the MI Data 0-1 Registers
and are output onto the MDIO pin and written to the external PHY. A
write operation is selected by appropriately setting the read/write select
bit in the MI Command/Status 1 register. After this bit is written, a write
MI data transfer cycle is initiated on the MDC and MDIO pins. After the
write MI cycle has completed and all data is successfully written out, the
MI status bit in the MI Command/Status 1 register is set to indicate that
the operation is complete. The interrupt pin is asserted after a write
operation has completed if the interrupt bit is set in the MI
Command/Status 1 register. After the completion of a write operation, the
MDC clock is turned off and MDIO is held high.
3.12.5 Read Operation
A read operation is defined to be an MI data transfer cycle where the last
16 bits of data in the frame are read from an external PHY and latched
into the device from the MDIO pin and internally stored in the MI Data 0-
1 Registers. A read operation is selected by appropriately setting the
read/write select bit in the MI Command/Status 1 register. After this bit
is written, then a read MI data transfer cycle is initiated on the MDC and
MDIO pins. After a read MI cycle has completed and all the data is
successfully loaded into the MI Data registers, the MI status bit in the MI
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