參數(shù)資料
型號： L84302
元件分類： 通用總線功能
英文描述： L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述： L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊，4月2日
文件頁數(shù)： 36/128頁
文件大?。?/td> 997K
代理商： L84302
36 of 128
April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
the interrupt function is enabled. Refer to
Section 3.9, “Packet Discard,”
page 41
for more information about discards. The device can also be
programmed to not discard and accept all receive undersize packets by
setting the undersize packet accept bit in the RX Command register.
If a receive packet contains dribble bits—that is, if the receive packet
contains a non-integer number of bytes—the condition is indicated by
setting the dribble error detect bit in the RX Status register.
3.5.9 RX Status Register
Each port contains one RX Status register which stores the status of the
last packet received. With each reception attempt, whether the packet is
discarded or not, the status register is written with the status for that
packet. When the RX Status register is written, the receive status update
bit is set in that register to indicate that the register contains new
information. The data remains latched in the RX Status register until it is
read out via the Register Interface. Thus, no new receive status for a
packet can be written until the register is read. When the RX Status
register is read, the receive status update bit is cleared low to indicate
that it does not contain new data since the last read. After the RX Status
register has been read, that register is available to be written with new
status information.
The bits in the RX Status register are a combination of error detect and
packet status bits. Bit 5 in the RX Status register indicates if the receive
packet had an error, i.e. is it good or not. If the receive packet had an
error, the error is reported in Bits 0-4 (FIFO overflow, CRC error,
undersize packet, oversize packet, and dribble error). Bit 6 indicates that
the first 12 bytes of the packet have been successfully received (the first
12 bytes contain the packet header). Bit 7 in the RX status register
indicates whether the register contain information on a new packet. All
the bits in the RX Status register are latched high, stay high until they
are read, and cleared low when read.
All the bits in the RX Status register assert interrupt with the exception
of the dribble error detect (Bit 2) and RX update (Bit 7) bits. An interrupt
caused by the good packet bit (Bit 5) and the receive first 12-Bytes bit
(Bit 6) is normally disabled, but it can be enabled by setting the
appropriate interrupt enable bits in the RX Command register. Interrupts
caused by all the receive bits can also be disabled by setting the receive
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