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參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 65/128頁 |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
65 of 128
April, 2002
mean both transmitted and received information because Ethernet
was originally a shared media protocol. As such, transmit packet and
octet counters are also available in counters #17-26 and can be
summed with the receive packet and octet counts if desired.
3.19 Register Interface
3.19.1 General
The Register Interface is a selectable 8/16-bit bidirectional data interface
that allows access to the internal registers.
3.19.2 Timing
The Register Interface consists of thirty seven signals: sixteen
bidirectional data I/O pins (CDST[15:0]), eight register address inputs
(A[7:0]), one chip select input (ENREGIO), one read select input (RD),
one write select input (WR), two port select inputs (REGPS[1:0], one bus
size select input (BUSSIZE), two byte enable inputs (BE[1:0]), one data
ready output (READY), and four interrupt outputs, one per port
(INT_[1:4]).
To access a register through the Register Interface, ENREGIO must first
be asserted active low. Then either RD or WR must be asserted active
low to indicate either a read or a write cycle. On that same falling edge
of either RD or WR, the address of the register that will be accessed
needs to be present on A[7:0], and the port to be selected must be
present on REGPS[1:0]. If the cycle is a write cycle (WR asserted), then
the data on CDST[15:0] will be written to the designated register. If the
cycle is a read cycle (RD asserted), then data from the designated
register will be output on CDST[15:0] after some delay after the falling
edge of RD. The READY output will then go active high to indicate that
the data on CDST[15:0] is valid. READY will stay high as long as RD is
asserted, and return low after RD is deasserted. READY is placed in high
impedance state when ENREGIO is deasserted and driven when
ENREGIO is asserted. ENREGIO can remain low for multiple read or
write cycles so that many registers can be read or written to in one
ENREGIO assertion.
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