- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367493 > L84302 L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 PDF資料下載
參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術手冊，4月2日 |
| 文件頁數(shù)： | 29/128頁 |
| 文件大小： | 997K |
| 代理商： | L84302 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當前第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
29 of 128
April, 2002
3.4.5 Interpacket Gap
The interval between packets is called the interpacket gap, also referred
to as IPG. The minimum IPG is controlled by the defer mechanism. The
defer mechanism is an internal algorithm which computes a defer time.
If packets from the transmit FIFO arrive at the transmit MAC sooner than
the defer time, the defer mechanism will add enough IPG time between
packets to equal the defer time value.
In Half Duplex mode, the defer time is defined as the time from the falling
edge of CRS to the next rising edge of TXEN (CRS is normally asserted
during half duplex mode transmission due to PHY loopback behavior). In
Full Duplex mode, the defer time is defined as the time from the falling
edge of TXEN to the next rising edge of TXEN.
The defer time is split into two separate periods. The first period is
programmable using the bits in the Transmit Defer register. The second
period is fixed. The total defer time, also referred to as minimum IPG is
determined by the following equations:
100 & 10 Mbps MII Mode:
t
DEFER
= INT((INT(t
D
/40)+5+DEFER)2)+2
10 Mbps Serial Mode:
t
DEFER
= INT((INT(t
D
/100)+17+DEFER/8)+2
t
DEFER
= Defer time in bytes
INT(x) = Use whole number portion of x
t
D
= Delay from falling edge of TXEN to falling edge of CRS
(Half Duplex)
= 0 (Full Duplex)
DEFER = Decimal value of Transmit Defer register bits DEFER[7:0]
The computed defer time (minimum IPG) values for each setting of the
transmit defer register bits are also shown in
Appendix A: L84302 IPG
Table
.
3.4.6 Transmit Control
Packet transmission by the MAC is initiated once the packet data has
exceeded the programmable Transmit Control threshold or an entire
相關PDF資料 |
PDF描述 |
|---|---|
| L8560 | Low-Power SLIC with Ringing |
| L8567 | SLIC for Peoples Republic of China Applications |
| L8567-32PLCC | Telecommunication IC |
| L8567-44PLCC | Telecommunication IC |
| L8574D | CAP 15PF 50V 5% C0G SMD-0402 TR-7-PA SN100 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| L8446-04 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-06 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-07 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-41 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
| L8446-42 | 制造商:HAMAMATSU 制造商全稱:Hamamatsu Corporation 功能描述:CW LASER DIODES |
發(fā)布緊急采購，3分鐘左右您將得到回復。