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參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術手冊，4月2日 |
| 文件頁數(shù)： | 26/128頁 |
| 文件大小： | 997K |
| 代理商： | L84302 |
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26 of 128
April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
RXTXBE[3:0] are clocked in on rising edges of SCLK along with each
RXTXDATA[31:0] data word and indicate to the device which bytes
contain the actual data. The correspondence between the byte enable
inputs and the valid bytes of each data word on RXTXDATA[31:0] is
defined in
Table 2
. Any logic combination of RXTXBE[3:0] inputs is
allowed, with the the exception that RXTXBE[3:0] must not be 1111.
The end of frame I/O pin, RXTXEOF, indicates which data word is the
last word of the Ethernet data packet. RXTXEOF is configured to be an
output during a receive read operation, and is output on the rising edges
of SCLK. The position of RXTXEOF during System Interface read
operations can be programmed to occur either (1) when the receive
status word is read out, or (2) when both the last data word of packet
and the receive status word are read out. This selection of either a single
RXTXEOF at status word or a double RXTXEOF at end of data and
status word is accomplished by appropriately setting the receive EOF
position select bit in the Configuration 2 register. The selection of the
EOF position is also affected by the setting of the status word disable bit
in Configuration 3 register. The EOF position as a function of both the
EOF position bit and status word disable bit is shown in
Table 3
. More
details about the status word can be found in the
Section 3.10, “Receive
Status Word,” page 43
.
There are four receive FIFO ready outputs, one per port, on the
RXRDY_[1:4] pins. The receive FIFO ready output is a receive FIFO
watermark signal which indicates when the receive FIFO data has
exceeded the programmable receive FIFO threshold value. RXRDY_[1:4]
will be asserted or deasserted by the device on rising edges of SCLK,
depending on the fullness of the receive FIFO. Refer to
Section 3.7,
“Receive FIFO,” page 39
, for more details on RXRDY_[1:4].
Table 3
RXTXEOF Position
PEOF
(Bit 2, Cfg Reg.2)
SWRD_DIS
(Bit 1, Cfg Reg.3)
RXTXEOF Position
0
0
Status Word
0
1
Data
1
0
Data & Status Word
1
1
Data
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