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參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 58/128頁 |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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58 of 128
April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
3.18.3 Counter Reset On Read
The counter value is normally unaffected by a read operation on that
counter. However, the counters can be programmed to automatically
reset the count to 0 when read out by setting the counter reset on read
bit in the Configuration 3 register. When this bit is set high, the counter
is reset to 0 when read out; when this bit is cleared low, the count inside
the counters is unaffected by a read as long as the counter is not at
maximum count. If a counter is at maximum count, its count is always
reset to 0’s when it is read out.
3.18.4 Counter Rollover
The counters normally rollover to 0 when they exceed their maximum
count (i.e. receive an increment when counter is at maximum count). The
counters can be programmed to freeze and stop counting once they
reach their maximum count by setting the counter rollover bit in the
Configuration 3 register.
3.18.5 Maximum Packet Size
The maximum packet size used for the management counter statistics
can be set to any value between 1518-1533 bytes by appropriately
setting the counter maximum packet size select bit in the Configuration
4 register and the maximum packet size select bits in Configuration 5
register. The maximum packet size default is 1518 bytes.
3.18.6 Counter Reset
All counters, for a given port, can be reset to all 0’s by setting and then
clearing the counter reset bit in the Configuration 4 register for that port.
Asserting the device reset pin RESET will also set the counter reset bits
to their default values of 1 and subsequently force the counters in all
ports to 0. When this device reset occurs, the counter reset bits will be
set to their default value of 1, and they must be cleared to 0, on each
port, in order for the counters on that port to be functional.
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