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參數(shù)資料
| 型號(hào)： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊(cè)，4月2日 |
| 文件頁(yè)數(shù)： | 22/128頁(yè) |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
3.3.3 Byte Order
The byte ordering of the RXTXDATA data bits is programmable by
appropriately setting the endian select bit in the Configuration 2 register.
The byte order shown in
Figure 4
is the little endian format (default). If
big endian format is selected, then the byte order shown in
Figure 4
is
reversed, that is, DA[0:7] occurs on pins RXTXDATA[24:31], DA[24:31]
occurs on pins RXTXDATAD[0:7], etc. This difference between little
endian and big endian format is illustrated in
Figure 5
. Note that the byte
order of the Status word appended to Receive Packets is not affected by
Big/Little Endian Selection
Figure 5
Little Endian vs. Big Endian Format
3.3.4 Transmit Write Operation
All receive and transmit data is clocked in/out on rising edges of the
system clock, SCLK. The SCLK input needs to be continuously input to
the device at a frequency between 25-50 MHz.
The System Interface is bidirectional. When it is configured for a transmit
write operation, data is input into the device and stored in the transmit
FIFO. A transmit write operation is initiated by asserting TXINTEN and
TXWREN. TXINTEN acts as a general transmit enable input, and
asserting TXINTEN also activates the output drivers for the TXRDY and
TXRET pins and removes them from high impedance state. Coincident
DA0..........................DA7
Little
Endian
(Default)
Preamble
A
A
RXTXDATA0............RXTXDATA7
DA8......................... DA15
RXTXDATA8...........RXTXDATA15
DA16.......................DA23
RXTXDATA16........... RXTXDATA23
DA40..................... DA47
Source Address
DA32 ..................... DA39
DA24......................DA31
RXTXDATA8 ...........RXTXDATA15
RXTXDATA16 ....
RXTXDATA24......... RXTXDATA31
RXTXDATA16........RXTXDATA23
RXTXDATA8.............RXTXDATA15
RXTXDATA0..........RXTXDATA7
RXTXDATA24........ RXTXDATA31
RXTXDATA16.........RXTXDATA23
RXTXDATA15.....
RXTXDATA24 .........RXTXDATA31
RXTXDATA0 ...........RXTXDATA7
Big
Endian
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