參數(shù)資料
型號: L84302
元件分類: 通用總線功能
英文描述: L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述: L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術手冊,4月2日
文件頁數(shù): 20/128頁
文件大?。?/td> 997K
代理商: L84302
20 of 128
April, 2002
L84302 Quad 4-Port Ethernet Controller - Technical Manual
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
one FIFO space/data available output (SPDTAVL)
four receive FIFO overflow indication outputs (RXOVF_[1:4], one per
port)
four receive FIFO abort inputs (RXABORT_[1:4], one per port).
All data is clocked in/out on rising edges of the system clock, SCLK.
SCLK can operate between 25 and 50 MHz.
3.3.2 Data Format and Bit Order
The format of the data word on RXTXDATA[31:0] and its relationship to
the MAC frame format and PHY Interface format is shown in
Figure 4
.
Note that the device can be programmed to append an additional 32-bit
status word to the end of the receive packet; refer to
Section 3.10,
“Receive Status Word,” page 43
, for more details on this status word.
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