參數(shù)資料
型號: L84302
元件分類: 通用總線功能
英文描述: L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述: L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊,4月2日
文件頁數(shù): 109/128頁
文件大?。?/td> 997K
代理商: L84302
Specifications
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
109 of 128
April, 2002
5.10 Receive PHY Interface Timing Characteristics
Refer to
Figure 15
for timing diagram.
Figure 15
Receive PHY Interface Timing
Sym.
Parameter
Limit
Unit
Conditions
Min
Typ
Max
t
81
RXC Cycle Time
1/25 - 0.01%
1/2.5 - 0.01%
1/10 - 0.01%
1/2 TXC Cycle
Time - 5 ns
1/2 TXC Cycle
Time - 5 ns
5
1/25
1/2.5
1/10
1/25 + 0.01%
1/2.5 + 0.01%
1/10 + 0.01%
1/MHz
1/MHz
1/MHz
ns
100 Mbps MII
100 Mbps MII
10 Mbps Serial
t
82
RXC HighTime
t
83
RXC Low Time
ns
t
84
RXD, RXDV, RXER
Setup Time
RXD, RXDV, RXER
Hold Time
ns
t
85
5
ns
t
84
t
81
t
82
t
83
RXC
t
84
t
85
CRS
RXDV
10 Mbytes Serial Mode
Same as MII Mode except:
(1) Data on RXD0 only
(2) RXDV not used
(3) RXER not used
t
85
t
84
t
85
RXD[3:0]
RXER
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