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| 型號(hào)： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊(cè)，4月2日 |
| 文件頁(yè)數(shù)： | 31/128頁(yè) |
| 文件大小： | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
31 of 128
April, 2002
The bits in the TX Status register are a combination of error detect and
packet status bits. Bit 3 in the TX Status register indicates if the transmit
packet had an error, i.e. was it successfully transmitted or not. If the
transmit packet was not successfully transmitted due to error, the error
is reported in Bits 0, 2, 4, and 6 (FIFO underflow, 16 collision error,
carrier sense error, and late collision). Bit 1 is a status bit and indicates
if a collision occurred during the transmission of the packet. Bit 5
indicates if the of the packet was deferred waiting for the completion of
receiving a packet. Bit 7 in the TX status register indicates whether the
register has been updated for a new packet since the last read. All the
bits in the TX Status register are latched high, stay high until they are
read, and cleared low when read.
All the bits in the TX Status register assert interrupt with the exception
of the defer detect (Bit 5) bit and the TX Status update bit (Bit 7).
Interrupts caused by all of these bits will normally be disabled but can be
enabled by setting the appropriate interrupt enable bits in the TX
Command register.
Table 14
summarizes all the bits that assert interrupt
and their associated enable/disable bits.
3.4.9 MAC Control Frame Generation
The transmit MAC can automatically generate and transmit MAC Control
Pause frames. MAC Control Pause frames are used for flow control. This
function is described in more detail in
Section 3.16, “MAC Control
Frames,” page 52
.
3.5 Receive MAC
3.5.1 General
The receive MAC (Media Access Control) section decomposes Ethernet
packets received from the receive MII by (1) stripping off the preamble &
SFD, (2) stripping off the CRC, (3) checking the destination address
against the address filters to determine packet validity, (4) checking
frame validity against the discard conditions, and (5) checking the
length/type field for MAC Control frames. Each of the above operations
can be individually disabled, if desired. The receive MAC then sends any
valid data to the receive FIFO for storage. The status of the last packet
received is available in the RX Status register.
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