參數(shù)資料
型號: L84302
元件分類: 通用總線功能
英文描述: L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02
中文描述: L84302四100/10 Mbps的4端口以太網(wǎng)的遠程監(jiān)控控制器/ SNMP管理處的技術手冊,4月2日
文件頁數(shù): 19/128頁
文件大?。?/td> 997K
代理商: L84302
Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
19 of 128
April, 2002
3.2.7 Frame Check Sequence
The frame check sequence (FCS), is a 32-bit cyclic redundancy check
(CRC) value computed on the entire frame, exclusive of preamble & SFD.
The FCS algorithm is defined in IEEE 802.3. The FCS is appended to
the end of the frame and is used to determine frame validity.
3.2.8 Interpacket Gap
The interpacket gap (IPG) is the time interval between packets. The
minimum IPG value is defined to be 96 bits, where 1 bit=10ns for 100
Mbps Ethernet & 1 bit=100ns for 10 Mbps Ethernet. There is no
maximum IPG limit.
3.3 System Interface
3.3.1 General
The System Interface is a 32-bit wide bidirectional parallel data interface.
Data to/from any of the four independent ports is input and output
through the System Interface.
The System Interface consists of 64 signals:
32 bidirectional data I/O (RXTXDATA[31:0])
four bidirectional byte enable I/O (RXTXBE[3:0])
one receive and one transmit enable input (RXINTEN and TXINTEN)
one receive read enable and one transmit write enable input
(RXRDEN and TXWREN)
two port select inputs (RXTXPS[1:0])
one bidirectional end of frame I/O (RXTXEOF)
one transmit and one receive FIFO watermark output (RXRDY and
TXRDY)
one transmit and one receive discard output (RXDC and TXRET)
one receive and one transmit discard clear input (CLR_RXERR and
CLRTXERR)
one transmit CRC enable input (TXNOCRC)
four flow control inputs (FCNTRL_[1:4], one per port)
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