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參數(shù)資料
| 型號： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊，4月2日 |
| 文件頁數(shù)： | 53/128頁 |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
53 of 128
April, 2002
3.16.2 Automatic Pause Frame Generation
MAC Control Pause frames can be automatically generated by asserting
the FCNTRL pin. When the FCNTRL pin is asserted, a series of Pause
frames will be internally generated and transmitted over the MII Interface.
These Pause frames are referred to as autogenerated Pause frames.
The transmission of autogenerated Pause frames is not affected by the
reception of a receive Pause frame; receive Pause frames only inhibit the
transmission of regular packets from the transmit FIFO.
If a packet transmission is in progress when the FCNTRL pin is asserted,
the device waits until the transmission of that packet has completed and
then transmits the autogenerated Pause frame before any other
subsequent packets in the TX FIFO are transmitted. When the first
autogenerated Pause frame begins transmission, an internal timer will
start, whose value is equal to the pause_time value in the Pause frame
(and obtained from Flow Control Pause Time 0-1 registers). If the
FCNTRL pin is still asserted when the internal pause timer expires, then
another autogenerated Pause frame will be transmitted. This process will
continue to repeat itself as long as FCNTRL remains asserted. When
FCNTRL is deasserted, then one last autogenerated Pause frame of
pause_time=0 will be transmitted. To compensate for latency, the internal
pause timer will be internally shorten itself by 32 units from the value
programmed into the Flow Control Pause Time 0-1 registers.
The device can be programmed to eliminate the last autogenerated
Pause frame with pause_time=0 by clearing low the MAC Control frame
end pause bit in the Configuration 4 register.
The structure of the autogenerated Pause frame is described in
Figure 7
.
Note that the source address and pause_time parameter fields are
programmable through internal registers as shown in
Figure 7
.
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