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| 型號(hào)： | L84302 |
| 元件分類： | 通用總線功能 |
| 英文描述： | L84302 Quad 100/10 Mbps 4-Port Ethernet Controller with RMON/SNMP Management Counters technical manual 4/02 |
| 中文描述： | L84302四100/10 Mbps的4端口以太網(wǎng)的遠(yuǎn)程監(jiān)控控制器/ SNMP管理處的技術(shù)手冊(cè)，4月2日 |
| 文件頁(yè)數(shù)： | 79/128頁(yè) |
| 文件大?。?/td> | 997K |
| 代理商： | L84302 |
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Functional Description
Copyright 1997-2002 by LSI Logic Corporation. All rights reserved.
79 of 128
April, 2002
Bit 0 occurs on CDST0/CDST8 pin
Table 24
Configuration 3 Register Definition
7
6
5
4
3
2
0
1
0
CTRROLL
R/W
CTRRD
R/W
TXSTS_COL
R/W
BOFFRST
R/W
ROWNT_OR
R/W
SWRD_DIS
R/W
BIDIRBE
R/W
R/W
Bit
Symbol
Name
Definition
R/W
Def.
7
CTRROLL
Counter Rollover
Stop Enable
1 = Counters stop at maximum count
0 = Counters roll over to 0 after maximum
count
R/W
0
6
CTRRD
Counter Reset
On Read Enable
1 = Counters reset to 0 when read (or 1 if
a count occurred during read)
0 = No reset on read
R/W
0
5
TXSTS_COL
Transmit Status
Disable On
Collision
1 = Transmit Status Register not updated if
collision occurs while packet is being
transmitted
0 = Updated
R/W
0
4
BOFFRST
Backoff Counter
Reset
1 = Normal
0 = Reset the polynomial counter used by
the transmitter to randomize the backoff
interval upon collision.
R/W
0
3
ROWNT_OR
ROWNTOverride
Select
1 = ROWNT bit (Bit 3, Config. 1 Reg.) is
forced to"0" when device is put in full
duplex mode
0 = Not forced
R/W
0
2
Reserved, must always be written to 0 for
proper operation
R/W
0
1
SWRD_DIS
Status Word
Disable
1 = Status word not appended to end of
receive packet
0 = Status word appended
R/W
0
0
BIDIRBE
Bidirectional Byte
Enable Select
1 = TXRXBE[3:0] pins are bidirectional, i.e.
inputs during TX FIFO writes and outputs
during RX FIFO reads.
0 = TXRXBE[3:0] Pins are always inputs,
i.e. inputs during TX FIFO writes and inputs
during RX FIFO reads.
R/W
0
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